Searched refs:MPLL_AD_FUNC_CNTL (Results 1 - 16 of 16) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h47 #define MPLL_AD_FUNC_CNTL 0x624 macro
H A Dradeon_rv740_dpm.c305 RREG32(MPLL_AD_FUNC_CNTL);
H A Drv770d.h120 #define MPLL_AD_FUNC_CNTL 0x624 macro
H A Dnid.h562 #define MPLL_AD_FUNC_CNTL 0x624 macro
H A Dcikd.h748 #define MPLL_AD_FUNC_CNTL 0x2bc0 macro
H A Dsid.h625 #define MPLL_AD_FUNC_CNTL 0x2bc0 macro
H A Dradeon_rv770_dpm.c1536 RREG32(MPLL_AD_FUNC_CNTL);
H A Devergreend.h100 #define MPLL_AD_FUNC_CNTL 0x624 macro
H A Dradeon_ni_dpm.c1195 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
H A Dradeon_ci_dpm.c1894 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
H A Dradeon_si_dpm.c3584 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h627 #define MPLL_AD_FUNC_CNTL 0xAF0 macro
H A Damdgpu_si_dpm.c4045 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c1088 /* MPLL_AD_FUNC_CNTL setup*/
1090 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
H A Damdgpu_ci_smumgr.c1063 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
H A Damdgpu_tonga_smumgr.c837 /* MPLL_AD_FUNC_CNTL setup*/
839 MPLL_AD_FUNC_CNTL, YCLK_POST_DIV,

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