Searched refs:CG_SPLL_FUNC_CNTL_3 (Results 1 - 19 of 19) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h39 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Drv730d.h42 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Dradeon_rv740_dpm.c298 RREG32(CG_SPLL_FUNC_CNTL_3);
H A Dradeon_rv730_dpm.c211 RREG32(CG_SPLL_FUNC_CNTL_3);
H A Drv770d.h106 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Dnid.h552 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Dcikd.h262 #define CG_SPLL_FUNC_CNTL_3 0xC0500148 macro
H A Dsid.h101 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Dradeon_rv770_dpm.c1530 RREG32(CG_SPLL_FUNC_CNTL_3);
H A Devergreend.h88 #define CG_SPLL_FUNC_CNTL_3 0x608 macro
H A Dradeon_ni_dpm.c1191 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
H A Dradeon_ci_dpm.c1885 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
H A Dradeon_si_dpm.c3578 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_fiji_smumgr.c898 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
902 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
H A Damdgpu_iceland_smumgr.c837 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
841 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
H A Damdgpu_ci_smumgr.c336 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
340 spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3, CG_SPLL_FUNC_CNTL_3,
H A Damdgpu_tonga_smumgr.c580 CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
584 CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h103 #define CG_SPLL_FUNC_CNTL_3 0x182 macro
H A Damdgpu_si_dpm.c4039 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);

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