Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 - 21 of 21) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv740d.h36 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv730d.h39 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dradeon_rv740_dpm.c296 RREG32(CG_SPLL_FUNC_CNTL_2);
H A Dradeon_rv730_dpm.c209 RREG32(CG_SPLL_FUNC_CNTL_2);
H A Dradeon_rv770.c1150 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
1153 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
1162 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
H A Drv770d.h102 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dnid.h549 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dcikd.h259 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
H A Dsid.h96 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dradeon_si.c4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
4012 tmp = RREG32(CG_SPLL_FUNC_CNTL_2);
4014 WREG32(CG_SPLL_FUNC_CNTL_2, tmp);
H A Dradeon_rv770_dpm.c1528 RREG32(CG_SPLL_FUNC_CNTL_2);
H A Devergreend.h84 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dradeon_ni_dpm.c1190 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
H A Dradeon_ci_dpm.c1883 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
H A Dradeon_si_dpm.c3577 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsid.h98 #define CG_SPLL_FUNC_CNTL_2 0x181 macro
H A Damdgpu_si_dpm.c4038 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_fiji_smumgr.c1354 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,
H A Damdgpu_iceland_smumgr.c1471 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
H A Damdgpu_ci_smumgr.c1423 CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
H A Damdgpu_tonga_smumgr.c1219 spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2, CG_SPLL_FUNC_CNTL_2,

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