Searched refs:N_REG_CLASSES (Results 1 - 25 of 99) sorted by relevance

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/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/
H A Dira.h25 extern int ira_available_class_regs[N_REG_CLASSES];
40 extern enum reg_class ira_reg_class_cover[N_REG_CLASSES];
45 extern enum reg_class ira_class_translate[N_REG_CLASSES];
51 extern int ira_reg_class_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
62 extern short ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
67 extern short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
71 extern int ira_class_hard_regs_num[N_REG_CLASSES];
H A Dreginfo.c143 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
152 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
156 unsigned int reg_class_size[N_REG_CLASSES];
159 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
163 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
167 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
185 char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MOD
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H A Dira-int.h123 int reg_pressure[N_REG_CLASSES];
745 extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
751 extern short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
757 [N_REG_CLASSES][NUM_MACHINE_MODES];
770 extern enum reg_class ira_important_classes[N_REG_CLASSES];
775 extern int ira_important_class_nums[N_REG_CLASSES];
782 extern enum reg_class ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES];
787 extern bool ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSE
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H A Dira.c363 short int ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
381 int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
416 short ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
420 int ira_class_hard_regs_num[N_REG_CLASSES];
426 short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
439 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
470 int ira_available_class_regs[N_REG_CLASSES];
479 for (i = 0; i < N_REG_CLASSES; i++)
515 for (cl = (int) N_REG_CLASSES
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H A Dhard-reg-set.h644 extern HARD_REG_SET reg_class_contents[N_REG_CLASSES];
648 extern unsigned int reg_class_size[N_REG_CLASSES];
652 extern enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
657 extern enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
662 extern enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
H A Dregs.h267 extern char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
269 typedef unsigned short move_table[N_REG_CLASSES];
H A Dloop-invariant.c68 int max_reg_pressure[N_REG_CLASSES];
1054 unsigned aregs_needed[N_REG_CLASSES];
1252 unsigned aregs_needed[N_REG_CLASSES], invno;
1320 unsigned i, regs_used, regs_needed[N_REG_CLASSES], new_regs[N_REG_CLASSES];
1585 static int curr_reg_pressure[N_REG_CLASSES];
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/
H A Dregclass.c157 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
167 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
172 unsigned int reg_class_size[N_REG_CLASSES];
176 static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
180 static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
185 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
190 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSE
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H A Dhard-reg-set.h461 extern HARD_REG_SET reg_class_contents[N_REG_CLASSES];
465 extern unsigned int reg_class_size[N_REG_CLASSES];
470 extern enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
475 extern enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/pa/
H A Dpa64-regs.h223 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
233 of length N_REG_CLASSES. Register 0, the "condition code" register,
H A Dpa32-regs.h292 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
302 of length N_REG_CLASSES. Register 0, the "condition code" register,
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/pa/
H A Dpa32-regs.h268 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
278 of length N_REG_CLASSES. Register 0, the "condition code" register,
H A Dpa64-regs.h223 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
233 of length N_REG_CLASSES. Register 0, the "condition code" register,
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/crx/
H A Dcrx.h184 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/moxie/
H A Dmoxie.h153 #define N_REG_CLASSES LIM_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/picochip/
H A Dpicochip.h306 #define N_REG_CLASSES (int) LIM_REG_CLASSES
301 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/vax/
H A Dvax.h222 #define N_REG_CLASSES (int) LIM_REG_CLASSES
250 of length N_REG_CLASSES. */
219 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/crx/
H A Dcrx.h184 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/fr30/
H A Dfr30.h290 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
283 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/lm32/
H A Dlm32.h209 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/m32c/
H A Dm32c.h349 #define N_REG_CLASSES LIM_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/spu/
H A Dspu.h211 #define N_REG_CLASSES (int) LIM_REG_CLASSES
205 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/external/gpl3/gcc/dist/gcc/config/stormy16/
H A Dstormy16.h206 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
198 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/fr30/
H A Dfr30.h291 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
284 #define N_REG_CLASSES macro
/netbsd-6-1-5-RELEASE/gnu/dist/gcc4/gcc/config/m32c/
H A Dm32c.h313 #define N_REG_CLASSES LIM_REG_CLASSES macro

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