1/* Compute register class preferences for pseudo-registers. 2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996 3 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 4 Free Software Foundation, Inc. 5 6This file is part of GCC. 7 8GCC is free software; you can redistribute it and/or modify it under 9the terms of the GNU General Public License as published by the Free 10Software Foundation; either version 2, or (at your option) any later 11version. 12 13GCC is distributed in the hope that it will be useful, but WITHOUT ANY 14WARRANTY; without even the implied warranty of MERCHANTABILITY or 15FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 16for more details. 17 18You should have received a copy of the GNU General Public License 19along with GCC; see the file COPYING. If not, write to the Free 20Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 2102110-1301, USA. */ 22 23 24/* This file contains two passes of the compiler: reg_scan and reg_class. 25 It also defines some tables of information about the hardware registers 26 and a function init_reg_sets to initialize the tables. */ 27 28#include "config.h" 29#include "system.h" 30#include "coretypes.h" 31#include "tm.h" 32#include "hard-reg-set.h" 33#include "rtl.h" 34#include "expr.h" 35#include "tm_p.h" 36#include "flags.h" 37#include "basic-block.h" 38#include "regs.h" 39#include "function.h" 40#include "insn-config.h" 41#include "recog.h" 42#include "reload.h" 43#include "real.h" 44#include "toplev.h" 45#include "output.h" 46#include "ggc.h" 47#include "timevar.h" 48#include "hashtab.h" 49 50static void init_reg_sets_1 (void); 51static void init_reg_autoinc (void); 52 53/* If we have auto-increment or auto-decrement and we can have secondary 54 reloads, we are not allowed to use classes requiring secondary 55 reloads for pseudos auto-incremented since reload can't handle it. */ 56 57#ifdef AUTO_INC_DEC 58#if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS) 59#define FORBIDDEN_INC_DEC_CLASSES 60#endif 61#endif 62 63/* Register tables used by many passes. */ 64 65/* Indexed by hard register number, contains 1 for registers 66 that are fixed use (stack pointer, pc, frame pointer, etc.). 67 These are the registers that cannot be used to allocate 68 a pseudo reg for general use. */ 69 70char fixed_regs[FIRST_PSEUDO_REGISTER]; 71 72/* Same info as a HARD_REG_SET. */ 73 74HARD_REG_SET fixed_reg_set; 75 76/* Data for initializing the above. */ 77 78static const char initial_fixed_regs[] = FIXED_REGISTERS; 79 80/* Indexed by hard register number, contains 1 for registers 81 that are fixed use or are clobbered by function calls. 82 These are the registers that cannot be used to allocate 83 a pseudo reg whose life crosses calls unless we are able 84 to save/restore them across the calls. */ 85 86char call_used_regs[FIRST_PSEUDO_REGISTER]; 87 88/* Same info as a HARD_REG_SET. */ 89 90HARD_REG_SET call_used_reg_set; 91 92/* HARD_REG_SET of registers we want to avoid caller saving. */ 93HARD_REG_SET losing_caller_save_reg_set; 94 95/* Data for initializing the above. */ 96 97static const char initial_call_used_regs[] = CALL_USED_REGISTERS; 98 99/* This is much like call_used_regs, except it doesn't have to 100 be a superset of FIXED_REGISTERS. This vector indicates 101 what is really call clobbered, and is used when defining 102 regs_invalidated_by_call. */ 103 104#ifdef CALL_REALLY_USED_REGISTERS 105char call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; 106#endif 107 108#ifdef CALL_REALLY_USED_REGISTERS 109#define CALL_REALLY_USED_REGNO_P(X) call_really_used_regs[X] 110#else 111#define CALL_REALLY_USED_REGNO_P(X) call_used_regs[X] 112#endif 113 114 115/* Indexed by hard register number, contains 1 for registers that are 116 fixed use or call used registers that cannot hold quantities across 117 calls even if we are willing to save and restore them. call fixed 118 registers are a subset of call used registers. */ 119 120char call_fixed_regs[FIRST_PSEUDO_REGISTER]; 121 122/* The same info as a HARD_REG_SET. */ 123 124HARD_REG_SET call_fixed_reg_set; 125 126/* Number of non-fixed registers. */ 127 128int n_non_fixed_regs; 129 130/* Indexed by hard register number, contains 1 for registers 131 that are being used for global register decls. 132 These must be exempt from ordinary flow analysis 133 and are also considered fixed. */ 134 135char global_regs[FIRST_PSEUDO_REGISTER]; 136 137/* Contains 1 for registers that are set or clobbered by calls. */ 138/* ??? Ideally, this would be just call_used_regs plus global_regs, but 139 for someone's bright idea to have call_used_regs strictly include 140 fixed_regs. Which leaves us guessing as to the set of fixed_regs 141 that are actually preserved. We know for sure that those associated 142 with the local stack frame are safe, but scant others. */ 143 144HARD_REG_SET regs_invalidated_by_call; 145 146/* Table of register numbers in the order in which to try to use them. */ 147#ifdef REG_ALLOC_ORDER 148int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; 149 150/* The inverse of reg_alloc_order. */ 151int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER]; 152#endif 153 154/* For each reg class, a HARD_REG_SET saying which registers are in it. */ 155 156HARD_REG_SET reg_class_contents[N_REG_CLASSES]; 157 158/* The same information, but as an array of unsigned ints. We copy from 159 these unsigned ints to the table above. We do this so the tm.h files 160 do not have to be aware of the wordsize for machines with <= 64 regs. 161 Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 162 163#define N_REG_INTS \ 164 ((FIRST_PSEUDO_REGISTER + (32 - 1)) / 32) 165 166static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS] 167 = REG_CLASS_CONTENTS; 168 169/* For each reg class, number of regs it contains. */ 170 171unsigned int reg_class_size[N_REG_CLASSES]; 172 173/* For each reg class, table listing all the containing classes. */ 174 175static enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; 176 177/* For each reg class, table listing all the classes contained in it. */ 178 179static enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; 180 181/* For each pair of reg classes, 182 a largest reg class contained in their union. */ 183 184enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; 185 186/* For each pair of reg classes, 187 the smallest reg class containing their union. */ 188 189enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES]; 190 191/* Array containing all of the register names. */ 192 193const char * reg_names[] = REGISTER_NAMES; 194 195/* Array containing all of the register class names. */ 196 197const char * reg_class_names[] = REG_CLASS_NAMES; 198 199/* For each hard register, the widest mode object that it can contain. 200 This will be a MODE_INT mode if the register can hold integers. Otherwise 201 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the 202 register. */ 203 204enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER]; 205 206/* 1 if there is a register of given mode. */ 207 208bool have_regs_of_mode [MAX_MACHINE_MODE]; 209 210/* 1 if class does contain register of given mode. */ 211 212static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE]; 213 214/* Maximum cost of moving from a register in one class to a register in 215 another class. Based on REGISTER_MOVE_COST. */ 216 217static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 218 219/* Similar, but here we don't have to move if the first index is a subset 220 of the second so in that case the cost is zero. */ 221 222static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 223 224/* Similar, but here we don't have to move if the first index is a superset 225 of the second so in that case the cost is zero. */ 226 227static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES]; 228 229#ifdef FORBIDDEN_INC_DEC_CLASSES 230 231/* These are the classes that regs which are auto-incremented or decremented 232 cannot be put in. */ 233 234static int forbidden_inc_dec_class[N_REG_CLASSES]; 235 236/* Indexed by n, is nonzero if (REG n) is used in an auto-inc or auto-dec 237 context. */ 238 239static char *in_inc_dec; 240 241#endif /* FORBIDDEN_INC_DEC_CLASSES */ 242 243/* Sample MEM values for use by memory_move_secondary_cost. */ 244 245static GTY(()) rtx top_of_stack[MAX_MACHINE_MODE]; 246 247/* Linked list of reg_info structures allocated for reg_n_info array. 248 Grouping all of the allocated structures together in one lump 249 means only one call to bzero to clear them, rather than n smaller 250 calls. */ 251struct reg_info_data { 252 struct reg_info_data *next; /* next set of reg_info structures */ 253 size_t min_index; /* minimum index # */ 254 size_t max_index; /* maximum index # */ 255 char used_p; /* nonzero if this has been used previously */ 256 reg_info data[1]; /* beginning of the reg_info data */ 257}; 258 259static struct reg_info_data *reg_info_head; 260 261/* No more global register variables may be declared; true once 262 regclass has been initialized. */ 263 264static int no_global_reg_vars = 0; 265 266/* Specify number of hard registers given machine mode occupy. */ 267unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE]; 268 269/* Function called only once to initialize the above data on reg usage. 270 Once this is done, various switches may override. */ 271 272void 273init_reg_sets (void) 274{ 275 int i, j; 276 277 /* First copy the register information from the initial int form into 278 the regsets. */ 279 280 for (i = 0; i < N_REG_CLASSES; i++) 281 { 282 CLEAR_HARD_REG_SET (reg_class_contents[i]); 283 284 /* Note that we hard-code 32 here, not HOST_BITS_PER_INT. */ 285 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 286 if (int_reg_class_contents[i][j / 32] 287 & ((unsigned) 1 << (j % 32))) 288 SET_HARD_REG_BIT (reg_class_contents[i], j); 289 } 290 291 /* Sanity check: make sure the target macros FIXED_REGISTERS and 292 CALL_USED_REGISTERS had the right number of initializers. */ 293 gcc_assert (sizeof fixed_regs == sizeof initial_fixed_regs); 294 gcc_assert (sizeof call_used_regs == sizeof initial_call_used_regs); 295 296 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs); 297 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs); 298 memset (global_regs, 0, sizeof global_regs); 299 300#ifdef REG_ALLOC_ORDER 301 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 302 inv_reg_alloc_order[reg_alloc_order[i]] = i; 303#endif 304} 305 306/* After switches have been processed, which perhaps alter 307 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ 308 309static void 310init_reg_sets_1 (void) 311{ 312 unsigned int i, j; 313 unsigned int /* enum machine_mode */ m; 314 315 /* This macro allows the fixed or call-used registers 316 and the register classes to depend on target flags. */ 317 318#ifdef CONDITIONAL_REGISTER_USAGE 319 CONDITIONAL_REGISTER_USAGE; 320#endif 321 322 /* Compute number of hard regs in each class. */ 323 324 memset (reg_class_size, 0, sizeof reg_class_size); 325 for (i = 0; i < N_REG_CLASSES; i++) 326 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 327 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 328 reg_class_size[i]++; 329 330 /* Initialize the table of subunions. 331 reg_class_subunion[I][J] gets the largest-numbered reg-class 332 that is contained in the union of classes I and J. */ 333 334 for (i = 0; i < N_REG_CLASSES; i++) 335 { 336 for (j = 0; j < N_REG_CLASSES; j++) 337 { 338 HARD_REG_SET c; 339 int k; 340 341 COPY_HARD_REG_SET (c, reg_class_contents[i]); 342 IOR_HARD_REG_SET (c, reg_class_contents[j]); 343 for (k = 0; k < N_REG_CLASSES; k++) 344 { 345 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, 346 subclass1); 347 continue; 348 349 subclass1: 350 /* Keep the largest subclass. */ /* SPEE 900308 */ 351 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], 352 reg_class_contents[(int) reg_class_subunion[i][j]], 353 subclass2); 354 reg_class_subunion[i][j] = (enum reg_class) k; 355 subclass2: 356 ; 357 } 358 } 359 } 360 361 /* Initialize the table of superunions. 362 reg_class_superunion[I][J] gets the smallest-numbered reg-class 363 containing the union of classes I and J. */ 364 365 for (i = 0; i < N_REG_CLASSES; i++) 366 { 367 for (j = 0; j < N_REG_CLASSES; j++) 368 { 369 HARD_REG_SET c; 370 int k; 371 372 COPY_HARD_REG_SET (c, reg_class_contents[i]); 373 IOR_HARD_REG_SET (c, reg_class_contents[j]); 374 for (k = 0; k < N_REG_CLASSES; k++) 375 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass); 376 377 superclass: 378 reg_class_superunion[i][j] = (enum reg_class) k; 379 } 380 } 381 382 /* Initialize the tables of subclasses and superclasses of each reg class. 383 First clear the whole table, then add the elements as they are found. */ 384 385 for (i = 0; i < N_REG_CLASSES; i++) 386 { 387 for (j = 0; j < N_REG_CLASSES; j++) 388 { 389 reg_class_superclasses[i][j] = LIM_REG_CLASSES; 390 reg_class_subclasses[i][j] = LIM_REG_CLASSES; 391 } 392 } 393 394 for (i = 0; i < N_REG_CLASSES; i++) 395 { 396 if (i == (int) NO_REGS) 397 continue; 398 399 for (j = i + 1; j < N_REG_CLASSES; j++) 400 { 401 enum reg_class *p; 402 403 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], 404 subclass); 405 continue; 406 subclass: 407 /* Reg class I is a subclass of J. 408 Add J to the table of superclasses of I. */ 409 p = ®_class_superclasses[i][0]; 410 while (*p != LIM_REG_CLASSES) p++; 411 *p = (enum reg_class) j; 412 /* Add I to the table of superclasses of J. */ 413 p = ®_class_subclasses[j][0]; 414 while (*p != LIM_REG_CLASSES) p++; 415 *p = (enum reg_class) i; 416 } 417 } 418 419 /* Initialize "constant" tables. */ 420 421 CLEAR_HARD_REG_SET (fixed_reg_set); 422 CLEAR_HARD_REG_SET (call_used_reg_set); 423 CLEAR_HARD_REG_SET (call_fixed_reg_set); 424 CLEAR_HARD_REG_SET (regs_invalidated_by_call); 425 426 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs); 427 428 n_non_fixed_regs = 0; 429 430 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 431 { 432 /* call_used_regs must include fixed_regs. */ 433 gcc_assert (!fixed_regs[i] || call_used_regs[i]); 434#ifdef CALL_REALLY_USED_REGISTERS 435 /* call_used_regs must include call_really_used_regs. */ 436 gcc_assert (!call_really_used_regs[i] || call_used_regs[i]); 437#endif 438 439 if (fixed_regs[i]) 440 SET_HARD_REG_BIT (fixed_reg_set, i); 441 else 442 n_non_fixed_regs++; 443 444 if (call_used_regs[i]) 445 SET_HARD_REG_BIT (call_used_reg_set, i); 446 if (call_fixed_regs[i]) 447 SET_HARD_REG_BIT (call_fixed_reg_set, i); 448 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i))) 449 SET_HARD_REG_BIT (losing_caller_save_reg_set, i); 450 451 /* There are a couple of fixed registers that we know are safe to 452 exclude from being clobbered by calls: 453 454 The frame pointer is always preserved across calls. The arg pointer 455 is if it is fixed. The stack pointer usually is, unless 456 RETURN_POPS_ARGS, in which case an explicit CLOBBER will be present. 457 If we are generating PIC code, the PIC offset table register is 458 preserved across calls, though the target can override that. */ 459 460 if (i == STACK_POINTER_REGNUM) 461 ; 462 else if (global_regs[i]) 463 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 464 else if (i == FRAME_POINTER_REGNUM) 465 ; 466#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 467 else if (i == HARD_FRAME_POINTER_REGNUM) 468 ; 469#endif 470#if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM 471 else if (i == ARG_POINTER_REGNUM && fixed_regs[i]) 472 ; 473#endif 474#ifndef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 475 else if (i == (unsigned) PIC_OFFSET_TABLE_REGNUM && fixed_regs[i]) 476 ; 477#endif 478 else if (CALL_REALLY_USED_REGNO_P (i)) 479 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 480 } 481 482 memset (have_regs_of_mode, 0, sizeof (have_regs_of_mode)); 483 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode)); 484 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 485 for (i = 0; i < N_REG_CLASSES; i++) 486 if ((unsigned) CLASS_MAX_NREGS (i, m) <= reg_class_size[i]) 487 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 488 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j) 489 && HARD_REGNO_MODE_OK (j, m)) 490 { 491 contains_reg_of_mode [i][m] = 1; 492 have_regs_of_mode [m] = 1; 493 break; 494 } 495 496 /* Initialize the move cost table. Find every subset of each class 497 and take the maximum cost of moving any subset to any other. */ 498 499 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++) 500 if (have_regs_of_mode [m]) 501 { 502 for (i = 0; i < N_REG_CLASSES; i++) 503 if (contains_reg_of_mode [i][m]) 504 for (j = 0; j < N_REG_CLASSES; j++) 505 { 506 int cost; 507 enum reg_class *p1, *p2; 508 509 if (!contains_reg_of_mode [j][m]) 510 { 511 move_cost[m][i][j] = 65536; 512 may_move_in_cost[m][i][j] = 65536; 513 may_move_out_cost[m][i][j] = 65536; 514 } 515 else 516 { 517 cost = REGISTER_MOVE_COST (m, i, j); 518 519 for (p2 = ®_class_subclasses[j][0]; 520 *p2 != LIM_REG_CLASSES; 521 p2++) 522 if (*p2 != i && contains_reg_of_mode [*p2][m]) 523 cost = MAX (cost, move_cost [m][i][*p2]); 524 525 for (p1 = ®_class_subclasses[i][0]; 526 *p1 != LIM_REG_CLASSES; 527 p1++) 528 if (*p1 != j && contains_reg_of_mode [*p1][m]) 529 cost = MAX (cost, move_cost [m][*p1][j]); 530 531 move_cost[m][i][j] = cost; 532 533 if (reg_class_subset_p (i, j)) 534 may_move_in_cost[m][i][j] = 0; 535 else 536 may_move_in_cost[m][i][j] = cost; 537 538 if (reg_class_subset_p (j, i)) 539 may_move_out_cost[m][i][j] = 0; 540 else 541 may_move_out_cost[m][i][j] = cost; 542 } 543 } 544 else 545 for (j = 0; j < N_REG_CLASSES; j++) 546 { 547 move_cost[m][i][j] = 65536; 548 may_move_in_cost[m][i][j] = 65536; 549 may_move_out_cost[m][i][j] = 65536; 550 } 551 } 552} 553 554/* Compute the table of register modes. 555 These values are used to record death information for individual registers 556 (as opposed to a multi-register mode). */ 557 558void 559init_reg_modes_once (void) 560{ 561 int i, j; 562 563 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 564 for (j = 0; j < MAX_MACHINE_MODE; j++) 565 hard_regno_nregs[i][j] = HARD_REGNO_NREGS(i, (enum machine_mode)j); 566 567 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 568 { 569 reg_raw_mode[i] = choose_hard_reg_mode (i, 1, false); 570 571 /* If we couldn't find a valid mode, just use the previous mode. 572 ??? One situation in which we need to do this is on the mips where 573 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like 574 to use DF mode for the even registers and VOIDmode for the odd 575 (for the cpu models where the odd ones are inaccessible). */ 576 if (reg_raw_mode[i] == VOIDmode) 577 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1]; 578 } 579} 580 581/* Finish initializing the register sets and 582 initialize the register modes. */ 583 584void 585init_regs (void) 586{ 587 /* This finishes what was started by init_reg_sets, but couldn't be done 588 until after register usage was specified. */ 589 init_reg_sets_1 (); 590 591 init_reg_autoinc (); 592} 593 594/* Initialize some fake stack-frame MEM references for use in 595 memory_move_secondary_cost. */ 596 597void 598init_fake_stack_mems (void) 599{ 600#ifdef HAVE_SECONDARY_RELOADS 601 { 602 int i; 603 604 for (i = 0; i < MAX_MACHINE_MODE; i++) 605 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx); 606 } 607#endif 608} 609 610#ifdef HAVE_SECONDARY_RELOADS 611 612/* Compute extra cost of moving registers to/from memory due to reloads. 613 Only needed if secondary reloads are required for memory moves. */ 614 615int 616memory_move_secondary_cost (enum machine_mode mode, enum reg_class class, int in) 617{ 618 enum reg_class altclass; 619 int partial_cost = 0; 620 /* We need a memory reference to feed to SECONDARY... macros. */ 621 /* mem may be unused even if the SECONDARY_ macros are defined. */ 622 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode]; 623 624 625 if (in) 626 { 627#ifdef SECONDARY_INPUT_RELOAD_CLASS 628 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem); 629#else 630 altclass = NO_REGS; 631#endif 632 } 633 else 634 { 635#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 636 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem); 637#else 638 altclass = NO_REGS; 639#endif 640 } 641 642 if (altclass == NO_REGS) 643 return 0; 644 645 if (in) 646 partial_cost = REGISTER_MOVE_COST (mode, altclass, class); 647 else 648 partial_cost = REGISTER_MOVE_COST (mode, class, altclass); 649 650 if (class == altclass) 651 /* This isn't simply a copy-to-temporary situation. Can't guess 652 what it is, so MEMORY_MOVE_COST really ought not to be calling 653 here in that case. 654 655 I'm tempted to put in an assert here, but returning this will 656 probably only give poor estimates, which is what we would've 657 had before this code anyways. */ 658 return partial_cost; 659 660 /* Check if the secondary reload register will also need a 661 secondary reload. */ 662 return memory_move_secondary_cost (mode, altclass, in) + partial_cost; 663} 664#endif 665 666/* Return a machine mode that is legitimate for hard reg REGNO and large 667 enough to save nregs. If we can't find one, return VOIDmode. 668 If CALL_SAVED is true, only consider modes that are call saved. */ 669 670enum machine_mode 671choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, 672 unsigned int nregs, bool call_saved) 673{ 674 unsigned int /* enum machine_mode */ m; 675 enum machine_mode found_mode = VOIDmode, mode; 676 677 /* We first look for the largest integer mode that can be validly 678 held in REGNO. If none, we look for the largest floating-point mode. 679 If we still didn't find a valid mode, try CCmode. */ 680 681 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 682 mode != VOIDmode; 683 mode = GET_MODE_WIDER_MODE (mode)) 684 if ((unsigned) hard_regno_nregs[regno][mode] == nregs 685 && HARD_REGNO_MODE_OK (regno, mode) 686 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 687 found_mode = mode; 688 689 if (found_mode != VOIDmode) 690 return found_mode; 691 692 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); 693 mode != VOIDmode; 694 mode = GET_MODE_WIDER_MODE (mode)) 695 if ((unsigned) hard_regno_nregs[regno][mode] == nregs 696 && HARD_REGNO_MODE_OK (regno, mode) 697 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 698 found_mode = mode; 699 700 if (found_mode != VOIDmode) 701 return found_mode; 702 703 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); 704 mode != VOIDmode; 705 mode = GET_MODE_WIDER_MODE (mode)) 706 if ((unsigned) hard_regno_nregs[regno][mode] == nregs 707 && HARD_REGNO_MODE_OK (regno, mode) 708 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 709 found_mode = mode; 710 711 if (found_mode != VOIDmode) 712 return found_mode; 713 714 for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); 715 mode != VOIDmode; 716 mode = GET_MODE_WIDER_MODE (mode)) 717 if ((unsigned) hard_regno_nregs[regno][mode] == nregs 718 && HARD_REGNO_MODE_OK (regno, mode) 719 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 720 found_mode = mode; 721 722 if (found_mode != VOIDmode) 723 return found_mode; 724 725 /* Iterate over all of the CCmodes. */ 726 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m) 727 { 728 mode = (enum machine_mode) m; 729 if ((unsigned) hard_regno_nregs[regno][mode] == nregs 730 && HARD_REGNO_MODE_OK (regno, mode) 731 && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) 732 return mode; 733 } 734 735 /* We can't find a mode valid for this register. */ 736 return VOIDmode; 737} 738 739/* Specify the usage characteristics of the register named NAME. 740 It should be a fixed register if FIXED and a 741 call-used register if CALL_USED. */ 742 743void 744fix_register (const char *name, int fixed, int call_used) 745{ 746 int i; 747 748 /* Decode the name and update the primary form of 749 the register info. */ 750 751 if ((i = decode_reg_name (name)) >= 0) 752 { 753 if ((i == STACK_POINTER_REGNUM 754#ifdef HARD_FRAME_POINTER_REGNUM 755 || i == HARD_FRAME_POINTER_REGNUM 756#else 757 || i == FRAME_POINTER_REGNUM 758#endif 759 ) 760 && (fixed == 0 || call_used == 0)) 761 { 762 static const char * const what_option[2][2] = { 763 { "call-saved", "call-used" }, 764 { "no-such-option", "fixed" }}; 765 766 error ("can't use '%s' as a %s register", name, 767 what_option[fixed][call_used]); 768 } 769 else 770 { 771 fixed_regs[i] = fixed; 772 call_used_regs[i] = call_used; 773#ifdef CALL_REALLY_USED_REGISTERS 774 if (fixed == 0) 775 call_really_used_regs[i] = call_used; 776#endif 777 } 778 } 779 else 780 { 781 warning (0, "unknown register name: %s", name); 782 } 783} 784 785/* Mark register number I as global. */ 786 787void 788globalize_reg (int i) 789{ 790 if (fixed_regs[i] == 0 && no_global_reg_vars) 791 error ("global register variable follows a function definition"); 792 793 if (global_regs[i]) 794 { 795 warning (0, "register used for two global register variables"); 796 return; 797 } 798 799 if (call_used_regs[i] && ! fixed_regs[i]) 800 warning (0, "call-clobbered register used for global register variable"); 801 802 global_regs[i] = 1; 803 804 /* If we're globalizing the frame pointer, we need to set the 805 appropriate regs_invalidated_by_call bit, even if it's already 806 set in fixed_regs. */ 807 if (i != STACK_POINTER_REGNUM) 808 SET_HARD_REG_BIT (regs_invalidated_by_call, i); 809 810 /* If already fixed, nothing else to do. */ 811 if (fixed_regs[i]) 812 return; 813 814 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1; 815#ifdef CALL_REALLY_USED_REGISTERS 816 call_really_used_regs[i] = 1; 817#endif 818 n_non_fixed_regs--; 819 820 SET_HARD_REG_BIT (fixed_reg_set, i); 821 SET_HARD_REG_BIT (call_used_reg_set, i); 822 SET_HARD_REG_BIT (call_fixed_reg_set, i); 823} 824 825/* Now the data and code for the `regclass' pass, which happens 826 just before local-alloc. */ 827 828/* The `costs' struct records the cost of using a hard register of each class 829 and of using memory for each pseudo. We use this data to set up 830 register class preferences. */ 831 832struct costs 833{ 834 int cost[N_REG_CLASSES]; 835 int mem_cost; 836}; 837 838/* Structure used to record preferences of given pseudo. */ 839struct reg_pref 840{ 841 /* (enum reg_class) prefclass is the preferred class. */ 842 char prefclass; 843 844 /* altclass is a register class that we should use for allocating 845 pseudo if no register in the preferred class is available. 846 If no register in this class is available, memory is preferred. 847 848 It might appear to be more general to have a bitmask of classes here, 849 but since it is recommended that there be a class corresponding to the 850 union of most major pair of classes, that generality is not required. */ 851 char altclass; 852}; 853 854/* Record the cost of each class for each pseudo. */ 855 856static struct costs *costs; 857 858/* Initialized once, and used to initialize cost values for each insn. */ 859 860static struct costs init_cost; 861 862/* Record preferences of each pseudo. 863 This is available after `regclass' is run. */ 864 865static struct reg_pref *reg_pref; 866 867/* Allocated buffers for reg_pref. */ 868 869static struct reg_pref *reg_pref_buffer; 870 871/* Frequency of executions of current insn. */ 872 873static int frequency; 874 875static rtx scan_one_insn (rtx, int); 876static void record_operand_costs (rtx, struct costs *, struct reg_pref *); 877static void dump_regclass (FILE *); 878static void record_reg_classes (int, int, rtx *, enum machine_mode *, 879 const char **, rtx, struct costs *, 880 struct reg_pref *); 881static int copy_cost (rtx, enum machine_mode, enum reg_class, int); 882static void record_address_regs (rtx, enum reg_class, int); 883#ifdef FORBIDDEN_INC_DEC_CLASSES 884static int auto_inc_dec_reg_p (rtx, enum machine_mode); 885#endif 886static void reg_scan_mark_refs (rtx, rtx, int, unsigned int); 887 888/* Return the reg_class in which pseudo reg number REGNO is best allocated. 889 This function is sometimes called before the info has been computed. 890 When that happens, just return GENERAL_REGS, which is innocuous. */ 891 892enum reg_class 893reg_preferred_class (int regno) 894{ 895 if (reg_pref == 0) 896 return GENERAL_REGS; 897 return (enum reg_class) reg_pref[regno].prefclass; 898} 899 900enum reg_class 901reg_alternate_class (int regno) 902{ 903 if (reg_pref == 0) 904 return ALL_REGS; 905 906 return (enum reg_class) reg_pref[regno].altclass; 907} 908 909/* Initialize some global data for this pass. */ 910 911void 912regclass_init (void) 913{ 914 int i; 915 916 init_cost.mem_cost = 10000; 917 for (i = 0; i < N_REG_CLASSES; i++) 918 init_cost.cost[i] = 10000; 919 920 /* This prevents dump_flow_info from losing if called 921 before regclass is run. */ 922 reg_pref = NULL; 923 924 /* No more global register variables may be declared. */ 925 no_global_reg_vars = 1; 926} 927 928/* Dump register costs. */ 929static void 930dump_regclass (FILE *dump) 931{ 932 int i; 933 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 934 { 935 int /* enum reg_class */ class; 936 if (REG_N_REFS (i)) 937 { 938 fprintf (dump, " Register %i costs:", i); 939 for (class = 0; class < (int) N_REG_CLASSES; class++) 940 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)] 941#ifdef FORBIDDEN_INC_DEC_CLASSES 942 && (!in_inc_dec[i] 943 || !forbidden_inc_dec_class[(enum reg_class) class]) 944#endif 945#ifdef CANNOT_CHANGE_MODE_CLASS 946 && ! invalid_mode_change_p (i, (enum reg_class) class, 947 PSEUDO_REGNO_MODE (i)) 948#endif 949 ) 950 fprintf (dump, " %s:%i", reg_class_names[class], 951 costs[i].cost[(enum reg_class) class]); 952 fprintf (dump, " MEM:%i\n", costs[i].mem_cost); 953 } 954 } 955} 956 957 958/* Calculate the costs of insn operands. */ 959 960static void 961record_operand_costs (rtx insn, struct costs *op_costs, 962 struct reg_pref *reg_pref) 963{ 964 const char *constraints[MAX_RECOG_OPERANDS]; 965 enum machine_mode modes[MAX_RECOG_OPERANDS]; 966 int i; 967 968 for (i = 0; i < recog_data.n_operands; i++) 969 { 970 constraints[i] = recog_data.constraints[i]; 971 modes[i] = recog_data.operand_mode[i]; 972 } 973 974 /* If we get here, we are set up to record the costs of all the 975 operands for this insn. Start by initializing the costs. 976 Then handle any address registers. Finally record the desired 977 classes for any pseudos, doing it twice if some pair of 978 operands are commutative. */ 979 980 for (i = 0; i < recog_data.n_operands; i++) 981 { 982 op_costs[i] = init_cost; 983 984 if (GET_CODE (recog_data.operand[i]) == SUBREG) 985 recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]); 986 987 if (MEM_P (recog_data.operand[i])) 988 record_address_regs (XEXP (recog_data.operand[i], 0), 989 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 990 else if (constraints[i][0] == 'p' 991 || EXTRA_ADDRESS_CONSTRAINT (constraints[i][0], constraints[i])) 992 record_address_regs (recog_data.operand[i], 993 MODE_BASE_REG_CLASS (modes[i]), frequency * 2); 994 } 995 996 /* Check for commutative in a separate loop so everything will 997 have been initialized. We must do this even if one operand 998 is a constant--see addsi3 in m68k.md. */ 999 1000 for (i = 0; i < (int) recog_data.n_operands - 1; i++) 1001 if (constraints[i][0] == '%') 1002 { 1003 const char *xconstraints[MAX_RECOG_OPERANDS]; 1004 int j; 1005 1006 /* Handle commutative operands by swapping the constraints. 1007 We assume the modes are the same. */ 1008 1009 for (j = 0; j < recog_data.n_operands; j++) 1010 xconstraints[j] = constraints[j]; 1011 1012 xconstraints[i] = constraints[i+1]; 1013 xconstraints[i+1] = constraints[i]; 1014 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1015 recog_data.operand, modes, 1016 xconstraints, insn, op_costs, reg_pref); 1017 } 1018 1019 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands, 1020 recog_data.operand, modes, 1021 constraints, insn, op_costs, reg_pref); 1022} 1023 1024/* Subroutine of regclass, processes one insn INSN. Scan it and record each 1025 time it would save code to put a certain register in a certain class. 1026 PASS, when nonzero, inhibits some optimizations which need only be done 1027 once. 1028 Return the last insn processed, so that the scan can be continued from 1029 there. */ 1030 1031static rtx 1032scan_one_insn (rtx insn, int pass) 1033{ 1034 enum rtx_code pat_code; 1035 rtx set, note; 1036 int i, j; 1037 struct costs op_costs[MAX_RECOG_OPERANDS]; 1038 1039 if (!INSN_P (insn)) 1040 return insn; 1041 1042 pat_code = GET_CODE (PATTERN (insn)); 1043 if (pat_code == USE 1044 || pat_code == CLOBBER 1045 || pat_code == ASM_INPUT 1046 || pat_code == ADDR_VEC 1047 || pat_code == ADDR_DIFF_VEC) 1048 return insn; 1049 1050 set = single_set (insn); 1051 extract_insn (insn); 1052 1053 /* If this insn loads a parameter from its stack slot, then 1054 it represents a savings, rather than a cost, if the 1055 parameter is stored in memory. Record this fact. */ 1056 1057 if (set != 0 && REG_P (SET_DEST (set)) 1058 && MEM_P (SET_SRC (set)) 1059 && (note = find_reg_note (insn, REG_EQUIV, 1060 NULL_RTX)) != 0 1061 && MEM_P (XEXP (note, 0))) 1062 { 1063 costs[REGNO (SET_DEST (set))].mem_cost 1064 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)), 1065 GENERAL_REGS, 1) 1066 * frequency); 1067 record_address_regs (XEXP (SET_SRC (set), 0), 1068 MODE_BASE_REG_CLASS (VOIDmode), frequency * 2); 1069 return insn; 1070 } 1071 1072 /* Improve handling of two-address insns such as 1073 (set X (ashift CONST Y)) where CONST must be made to 1074 match X. Change it into two insns: (set X CONST) 1075 (set X (ashift X Y)). If we left this for reloading, it 1076 would probably get three insns because X and Y might go 1077 in the same place. This prevents X and Y from receiving 1078 the same hard reg. 1079 1080 We can only do this if the modes of operands 0 and 1 1081 (which might not be the same) are tieable and we only need 1082 do this during our first pass. */ 1083 1084 if (pass == 0 && optimize 1085 && recog_data.n_operands >= 3 1086 && recog_data.constraints[1][0] == '0' 1087 && recog_data.constraints[1][1] == 0 1088 && CONSTANT_P (recog_data.operand[1]) 1089 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1]) 1090 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2]) 1091 && REG_P (recog_data.operand[0]) 1092 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]), 1093 recog_data.operand_mode[1])) 1094 { 1095 rtx previnsn = prev_real_insn (insn); 1096 rtx dest 1097 = gen_lowpart (recog_data.operand_mode[1], 1098 recog_data.operand[0]); 1099 rtx newinsn 1100 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn); 1101 1102 /* If this insn was the start of a basic block, 1103 include the new insn in that block. 1104 We need not check for code_label here; 1105 while a basic block can start with a code_label, 1106 INSN could not be at the beginning of that block. */ 1107 if (previnsn == 0 || JUMP_P (previnsn)) 1108 { 1109 basic_block b; 1110 FOR_EACH_BB (b) 1111 if (insn == BB_HEAD (b)) 1112 BB_HEAD (b) = newinsn; 1113 } 1114 1115 /* This makes one more setting of new insns's dest. */ 1116 REG_N_SETS (REGNO (recog_data.operand[0]))++; 1117 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1118 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1119 1120 *recog_data.operand_loc[1] = recog_data.operand[0]; 1121 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1122 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1123 for (i = recog_data.n_dups - 1; i >= 0; i--) 1124 if (recog_data.dup_num[i] == 1) 1125 { 1126 *recog_data.dup_loc[i] = recog_data.operand[0]; 1127 REG_N_REFS (REGNO (recog_data.operand[0]))++; 1128 REG_FREQ (REGNO (recog_data.operand[0])) += frequency; 1129 } 1130 1131 return PREV_INSN (newinsn); 1132 } 1133 1134 record_operand_costs (insn, op_costs, reg_pref); 1135 1136 /* Now add the cost for each operand to the total costs for 1137 its register. */ 1138 1139 for (i = 0; i < recog_data.n_operands; i++) 1140 if (REG_P (recog_data.operand[i]) 1141 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER) 1142 { 1143 int regno = REGNO (recog_data.operand[i]); 1144 struct costs *p = &costs[regno], *q = &op_costs[i]; 1145 1146 p->mem_cost += q->mem_cost * frequency; 1147 for (j = 0; j < N_REG_CLASSES; j++) 1148 p->cost[j] += q->cost[j] * frequency; 1149 } 1150 1151 return insn; 1152} 1153 1154/* Initialize information about which register classes can be used for 1155 pseudos that are auto-incremented or auto-decremented. */ 1156 1157static void 1158init_reg_autoinc (void) 1159{ 1160#ifdef FORBIDDEN_INC_DEC_CLASSES 1161 int i; 1162 1163 for (i = 0; i < N_REG_CLASSES; i++) 1164 { 1165 rtx r = gen_rtx_raw_REG (VOIDmode, 0); 1166 enum machine_mode m; 1167 int j; 1168 1169 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1170 if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) 1171 { 1172 REGNO (r) = j; 1173 1174 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE; 1175 m = (enum machine_mode) ((int) m + 1)) 1176 if (HARD_REGNO_MODE_OK (j, m)) 1177 { 1178 PUT_MODE (r, m); 1179 1180 /* If a register is not directly suitable for an 1181 auto-increment or decrement addressing mode and 1182 requires secondary reloads, disallow its class from 1183 being used in such addresses. */ 1184 1185 if ((0 1186#ifdef SECONDARY_RELOAD_CLASS 1187 || (SECONDARY_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1188 != NO_REGS) 1189#else 1190#ifdef SECONDARY_INPUT_RELOAD_CLASS 1191 || (SECONDARY_INPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1192 != NO_REGS) 1193#endif 1194#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1195 || (SECONDARY_OUTPUT_RELOAD_CLASS (MODE_BASE_REG_CLASS (VOIDmode), m, r) 1196 != NO_REGS) 1197#endif 1198#endif 1199 ) 1200 && ! auto_inc_dec_reg_p (r, m)) 1201 forbidden_inc_dec_class[i] = 1; 1202 } 1203 } 1204 } 1205#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1206} 1207 1208/* This is a pass of the compiler that scans all instructions 1209 and calculates the preferred class for each pseudo-register. 1210 This information can be accessed later by calling `reg_preferred_class'. 1211 This pass comes just before local register allocation. */ 1212 1213void 1214regclass (rtx f, int nregs, FILE *dump) 1215{ 1216 rtx insn; 1217 int i; 1218 int pass; 1219 1220 init_recog (); 1221 1222 costs = xmalloc (nregs * sizeof (struct costs)); 1223 1224#ifdef FORBIDDEN_INC_DEC_CLASSES 1225 1226 in_inc_dec = xmalloc (nregs); 1227 1228#endif /* FORBIDDEN_INC_DEC_CLASSES */ 1229 1230 /* Normally we scan the insns once and determine the best class to use for 1231 each register. However, if -fexpensive_optimizations are on, we do so 1232 twice, the second time using the tentative best classes to guide the 1233 selection. */ 1234 1235 for (pass = 0; pass <= flag_expensive_optimizations; pass++) 1236 { 1237 basic_block bb; 1238 1239 if (dump) 1240 fprintf (dump, "\n\nPass %i\n\n",pass); 1241 /* Zero out our accumulation of the cost of each class for each reg. */ 1242 1243 memset (costs, 0, nregs * sizeof (struct costs)); 1244 1245#ifdef FORBIDDEN_INC_DEC_CLASSES 1246 memset (in_inc_dec, 0, nregs); 1247#endif 1248 1249 /* Scan the instructions and record each time it would 1250 save code to put a certain register in a certain class. */ 1251 1252 if (!optimize) 1253 { 1254 frequency = REG_FREQ_MAX; 1255 for (insn = f; insn; insn = NEXT_INSN (insn)) 1256 insn = scan_one_insn (insn, pass); 1257 } 1258 else 1259 FOR_EACH_BB (bb) 1260 { 1261 /* Show that an insn inside a loop is likely to be executed three 1262 times more than insns outside a loop. This is much more 1263 aggressive than the assumptions made elsewhere and is being 1264 tried as an experiment. */ 1265 frequency = REG_FREQ_FROM_BB (bb); 1266 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) 1267 { 1268 insn = scan_one_insn (insn, pass); 1269 if (insn == BB_END (bb)) 1270 break; 1271 } 1272 } 1273 1274 /* Now for each register look at how desirable each class is 1275 and find which class is preferred. Store that in 1276 `prefclass'. Record in `altclass' the largest register 1277 class any of whose registers is better than memory. */ 1278 1279 if (pass == 0) 1280 reg_pref = reg_pref_buffer; 1281 1282 if (dump) 1283 { 1284 dump_regclass (dump); 1285 fprintf (dump,"\n"); 1286 } 1287 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) 1288 { 1289 int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1; 1290 enum reg_class best = ALL_REGS, alt = NO_REGS; 1291 /* This is an enum reg_class, but we call it an int 1292 to save lots of casts. */ 1293 int class; 1294 struct costs *p = &costs[i]; 1295 1296 /* In non-optimizing compilation REG_N_REFS is not initialized 1297 yet. */ 1298 if (optimize && !REG_N_REFS (i) && !REG_N_SETS (i)) 1299 continue; 1300 1301 for (class = (int) ALL_REGS - 1; class > 0; class--) 1302 { 1303 /* Ignore classes that are too small for this operand or 1304 invalid for an operand that was auto-incremented. */ 1305 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)] 1306#ifdef FORBIDDEN_INC_DEC_CLASSES 1307 || (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1308#endif 1309#ifdef CANNOT_CHANGE_MODE_CLASS 1310 || invalid_mode_change_p (i, (enum reg_class) class, 1311 PSEUDO_REGNO_MODE (i)) 1312#endif 1313 ) 1314 ; 1315 else if (p->cost[class] < best_cost) 1316 { 1317 best_cost = p->cost[class]; 1318 best = (enum reg_class) class; 1319 } 1320 else if (p->cost[class] == best_cost) 1321 best = reg_class_subunion[(int) best][class]; 1322 } 1323 1324 /* Record the alternate register class; i.e., a class for which 1325 every register in it is better than using memory. If adding a 1326 class would make a smaller class (i.e., no union of just those 1327 classes exists), skip that class. The major unions of classes 1328 should be provided as a register class. Don't do this if we 1329 will be doing it again later. */ 1330 1331 if ((pass == 1 || dump) || ! flag_expensive_optimizations) 1332 for (class = 0; class < N_REG_CLASSES; class++) 1333 if (p->cost[class] < p->mem_cost 1334 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]] 1335 > reg_class_size[(int) alt]) 1336#ifdef FORBIDDEN_INC_DEC_CLASSES 1337 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class]) 1338#endif 1339#ifdef CANNOT_CHANGE_MODE_CLASS 1340 && ! invalid_mode_change_p (i, (enum reg_class) class, 1341 PSEUDO_REGNO_MODE (i)) 1342#endif 1343 ) 1344 alt = reg_class_subunion[(int) alt][class]; 1345 1346 /* If we don't add any classes, nothing to try. */ 1347 if (alt == best) 1348 alt = NO_REGS; 1349 1350 if (dump 1351 && (reg_pref[i].prefclass != (int) best 1352 || reg_pref[i].altclass != (int) alt)) 1353 { 1354 fprintf (dump, " Register %i", i); 1355 if (alt == ALL_REGS || best == ALL_REGS) 1356 fprintf (dump, " pref %s\n", reg_class_names[(int) best]); 1357 else if (alt == NO_REGS) 1358 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]); 1359 else 1360 fprintf (dump, " pref %s, else %s\n", 1361 reg_class_names[(int) best], 1362 reg_class_names[(int) alt]); 1363 } 1364 1365 /* We cast to (int) because (char) hits bugs in some compilers. */ 1366 reg_pref[i].prefclass = (int) best; 1367 reg_pref[i].altclass = (int) alt; 1368 } 1369 } 1370 1371#ifdef FORBIDDEN_INC_DEC_CLASSES 1372 free (in_inc_dec); 1373#endif 1374 free (costs); 1375} 1376 1377/* Record the cost of using memory or registers of various classes for 1378 the operands in INSN. 1379 1380 N_ALTS is the number of alternatives. 1381 1382 N_OPS is the number of operands. 1383 1384 OPS is an array of the operands. 1385 1386 MODES are the modes of the operands, in case any are VOIDmode. 1387 1388 CONSTRAINTS are the constraints to use for the operands. This array 1389 is modified by this procedure. 1390 1391 This procedure works alternative by alternative. For each alternative 1392 we assume that we will be able to allocate all pseudos to their ideal 1393 register class and calculate the cost of using that alternative. Then 1394 we compute for each operand that is a pseudo-register, the cost of 1395 having the pseudo allocated to each register class and using it in that 1396 alternative. To this cost is added the cost of the alternative. 1397 1398 The cost of each class for this insn is its lowest cost among all the 1399 alternatives. */ 1400 1401static void 1402record_reg_classes (int n_alts, int n_ops, rtx *ops, 1403 enum machine_mode *modes, const char **constraints, 1404 rtx insn, struct costs *op_costs, 1405 struct reg_pref *reg_pref) 1406{ 1407 int alt; 1408 int i, j; 1409 rtx set; 1410 1411 /* Process each alternative, each time minimizing an operand's cost with 1412 the cost for each operand in that alternative. */ 1413 1414 for (alt = 0; alt < n_alts; alt++) 1415 { 1416 struct costs this_op_costs[MAX_RECOG_OPERANDS]; 1417 int alt_fail = 0; 1418 int alt_cost = 0; 1419 enum reg_class classes[MAX_RECOG_OPERANDS]; 1420 int allows_mem[MAX_RECOG_OPERANDS]; 1421 int class; 1422 1423 for (i = 0; i < n_ops; i++) 1424 { 1425 const char *p = constraints[i]; 1426 rtx op = ops[i]; 1427 enum machine_mode mode = modes[i]; 1428 int allows_addr = 0; 1429 int win = 0; 1430 unsigned char c; 1431 1432 /* Initially show we know nothing about the register class. */ 1433 classes[i] = NO_REGS; 1434 allows_mem[i] = 0; 1435 1436 /* If this operand has no constraints at all, we can conclude 1437 nothing about it since anything is valid. */ 1438 1439 if (*p == 0) 1440 { 1441 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1442 memset (&this_op_costs[i], 0, sizeof this_op_costs[i]); 1443 1444 continue; 1445 } 1446 1447 /* If this alternative is only relevant when this operand 1448 matches a previous operand, we do different things depending 1449 on whether this operand is a pseudo-reg or not. We must process 1450 any modifiers for the operand before we can make this test. */ 1451 1452 while (*p == '%' || *p == '=' || *p == '+' || *p == '&') 1453 p++; 1454 1455 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0)) 1456 { 1457 /* Copy class and whether memory is allowed from the matching 1458 alternative. Then perform any needed cost computations 1459 and/or adjustments. */ 1460 j = p[0] - '0'; 1461 classes[i] = classes[j]; 1462 allows_mem[i] = allows_mem[j]; 1463 1464 if (!REG_P (op) || REGNO (op) < FIRST_PSEUDO_REGISTER) 1465 { 1466 /* If this matches the other operand, we have no added 1467 cost and we win. */ 1468 if (rtx_equal_p (ops[j], op)) 1469 win = 1; 1470 1471 /* If we can put the other operand into a register, add to 1472 the cost of this alternative the cost to copy this 1473 operand to the register used for the other operand. */ 1474 1475 else if (classes[j] != NO_REGS) 1476 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1; 1477 } 1478 else if (!REG_P (ops[j]) 1479 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER) 1480 { 1481 /* This op is a pseudo but the one it matches is not. */ 1482 1483 /* If we can't put the other operand into a register, this 1484 alternative can't be used. */ 1485 1486 if (classes[j] == NO_REGS) 1487 alt_fail = 1; 1488 1489 /* Otherwise, add to the cost of this alternative the cost 1490 to copy the other operand to the register used for this 1491 operand. */ 1492 1493 else 1494 alt_cost += copy_cost (ops[j], mode, classes[j], 1); 1495 } 1496 else 1497 { 1498 /* The costs of this operand are not the same as the other 1499 operand since move costs are not symmetric. Moreover, 1500 if we cannot tie them, this alternative needs to do a 1501 copy, which is one instruction. */ 1502 1503 struct costs *pp = &this_op_costs[i]; 1504 1505 for (class = 0; class < N_REG_CLASSES; class++) 1506 pp->cost[class] 1507 = ((recog_data.operand_type[i] != OP_OUT 1508 ? may_move_in_cost[mode][class][(int) classes[i]] 1509 : 0) 1510 + (recog_data.operand_type[i] != OP_IN 1511 ? may_move_out_cost[mode][(int) classes[i]][class] 1512 : 0)); 1513 1514 /* If the alternative actually allows memory, make things 1515 a bit cheaper since we won't need an extra insn to 1516 load it. */ 1517 1518 pp->mem_cost 1519 = ((recog_data.operand_type[i] != OP_IN 1520 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1521 : 0) 1522 + (recog_data.operand_type[i] != OP_OUT 1523 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1524 : 0) - allows_mem[i]); 1525 1526 /* If we have assigned a class to this register in our 1527 first pass, add a cost to this alternative corresponding 1528 to what we would add if this register were not in the 1529 appropriate class. */ 1530 1531 if (reg_pref) 1532 alt_cost 1533 += (may_move_in_cost[mode] 1534 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1535 [(int) classes[i]]); 1536 1537 if (REGNO (ops[i]) != REGNO (ops[j]) 1538 && ! find_reg_note (insn, REG_DEAD, op)) 1539 alt_cost += 2; 1540 1541 /* This is in place of ordinary cost computation 1542 for this operand, so skip to the end of the 1543 alternative (should be just one character). */ 1544 while (*p && *p++ != ',') 1545 ; 1546 1547 constraints[i] = p; 1548 continue; 1549 } 1550 } 1551 1552 /* Scan all the constraint letters. See if the operand matches 1553 any of the constraints. Collect the valid register classes 1554 and see if this operand accepts memory. */ 1555 1556 while ((c = *p)) 1557 { 1558 switch (c) 1559 { 1560 case ',': 1561 break; 1562 case '*': 1563 /* Ignore the next letter for this pass. */ 1564 c = *++p; 1565 break; 1566 1567 case '?': 1568 alt_cost += 2; 1569 case '!': case '#': case '&': 1570 case '0': case '1': case '2': case '3': case '4': 1571 case '5': case '6': case '7': case '8': case '9': 1572 break; 1573 1574 case 'p': 1575 allows_addr = 1; 1576 win = address_operand (op, GET_MODE (op)); 1577 /* We know this operand is an address, so we want it to be 1578 allocated to a register that can be the base of an 1579 address, i.e. BASE_REG_CLASS. */ 1580 classes[i] 1581 = reg_class_subunion[(int) classes[i]] 1582 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1583 break; 1584 1585 case 'm': case 'o': case 'V': 1586 /* It doesn't seem worth distinguishing between offsettable 1587 and non-offsettable addresses here. */ 1588 allows_mem[i] = 1; 1589 if (MEM_P (op)) 1590 win = 1; 1591 break; 1592 1593 case '<': 1594 if (MEM_P (op) 1595 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1596 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1597 win = 1; 1598 break; 1599 1600 case '>': 1601 if (MEM_P (op) 1602 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1603 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1604 win = 1; 1605 break; 1606 1607 case 'E': 1608 case 'F': 1609 if (GET_CODE (op) == CONST_DOUBLE 1610 || (GET_CODE (op) == CONST_VECTOR 1611 && (GET_MODE_CLASS (GET_MODE (op)) 1612 == MODE_VECTOR_FLOAT))) 1613 win = 1; 1614 break; 1615 1616 case 'G': 1617 case 'H': 1618 if (GET_CODE (op) == CONST_DOUBLE 1619 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) 1620 win = 1; 1621 break; 1622 1623 case 's': 1624 if (GET_CODE (op) == CONST_INT 1625 || (GET_CODE (op) == CONST_DOUBLE 1626 && GET_MODE (op) == VOIDmode)) 1627 break; 1628 case 'i': 1629 if (CONSTANT_P (op) 1630 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))) 1631 win = 1; 1632 break; 1633 1634 case 'n': 1635 if (GET_CODE (op) == CONST_INT 1636 || (GET_CODE (op) == CONST_DOUBLE 1637 && GET_MODE (op) == VOIDmode)) 1638 win = 1; 1639 break; 1640 1641 case 'I': 1642 case 'J': 1643 case 'K': 1644 case 'L': 1645 case 'M': 1646 case 'N': 1647 case 'O': 1648 case 'P': 1649 if (GET_CODE (op) == CONST_INT 1650 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) 1651 win = 1; 1652 break; 1653 1654 case 'X': 1655 win = 1; 1656 break; 1657 1658 case 'g': 1659 if (MEM_P (op) 1660 || (CONSTANT_P (op) 1661 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)))) 1662 win = 1; 1663 allows_mem[i] = 1; 1664 case 'r': 1665 classes[i] 1666 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS]; 1667 break; 1668 1669 default: 1670 if (REG_CLASS_FROM_CONSTRAINT (c, p) != NO_REGS) 1671 classes[i] 1672 = reg_class_subunion[(int) classes[i]] 1673 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)]; 1674#ifdef EXTRA_CONSTRAINT_STR 1675 else if (EXTRA_CONSTRAINT_STR (op, c, p)) 1676 win = 1; 1677 1678 if (EXTRA_MEMORY_CONSTRAINT (c, p)) 1679 { 1680 /* Every MEM can be reloaded to fit. */ 1681 allows_mem[i] = 1; 1682 if (MEM_P (op)) 1683 win = 1; 1684 } 1685 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) 1686 { 1687 /* Every address can be reloaded to fit. */ 1688 allows_addr = 1; 1689 if (address_operand (op, GET_MODE (op))) 1690 win = 1; 1691 /* We know this operand is an address, so we want it to 1692 be allocated to a register that can be the base of an 1693 address, i.e. BASE_REG_CLASS. */ 1694 classes[i] 1695 = reg_class_subunion[(int) classes[i]] 1696 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1697 } 1698#endif 1699 break; 1700 } 1701 p += CONSTRAINT_LEN (c, p); 1702 if (c == ',') 1703 break; 1704 } 1705 1706 constraints[i] = p; 1707 1708 /* How we account for this operand now depends on whether it is a 1709 pseudo register or not. If it is, we first check if any 1710 register classes are valid. If not, we ignore this alternative, 1711 since we want to assume that all pseudos get allocated for 1712 register preferencing. If some register class is valid, compute 1713 the costs of moving the pseudo into that class. */ 1714 1715 if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER) 1716 { 1717 if (classes[i] == NO_REGS) 1718 { 1719 /* We must always fail if the operand is a REG, but 1720 we did not find a suitable class. 1721 1722 Otherwise we may perform an uninitialized read 1723 from this_op_costs after the `continue' statement 1724 below. */ 1725 alt_fail = 1; 1726 } 1727 else 1728 { 1729 struct costs *pp = &this_op_costs[i]; 1730 1731 for (class = 0; class < N_REG_CLASSES; class++) 1732 pp->cost[class] 1733 = ((recog_data.operand_type[i] != OP_OUT 1734 ? may_move_in_cost[mode][class][(int) classes[i]] 1735 : 0) 1736 + (recog_data.operand_type[i] != OP_IN 1737 ? may_move_out_cost[mode][(int) classes[i]][class] 1738 : 0)); 1739 1740 /* If the alternative actually allows memory, make things 1741 a bit cheaper since we won't need an extra insn to 1742 load it. */ 1743 1744 pp->mem_cost 1745 = ((recog_data.operand_type[i] != OP_IN 1746 ? MEMORY_MOVE_COST (mode, classes[i], 0) 1747 : 0) 1748 + (recog_data.operand_type[i] != OP_OUT 1749 ? MEMORY_MOVE_COST (mode, classes[i], 1) 1750 : 0) - allows_mem[i]); 1751 1752 /* If we have assigned a class to this register in our 1753 first pass, add a cost to this alternative corresponding 1754 to what we would add if this register were not in the 1755 appropriate class. */ 1756 1757 if (reg_pref) 1758 alt_cost 1759 += (may_move_in_cost[mode] 1760 [(unsigned char) reg_pref[REGNO (op)].prefclass] 1761 [(int) classes[i]]); 1762 } 1763 } 1764 1765 /* Otherwise, if this alternative wins, either because we 1766 have already determined that or if we have a hard register of 1767 the proper class, there is no cost for this alternative. */ 1768 1769 else if (win 1770 || (REG_P (op) 1771 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op)))) 1772 ; 1773 1774 /* If registers are valid, the cost of this alternative includes 1775 copying the object to and/or from a register. */ 1776 1777 else if (classes[i] != NO_REGS) 1778 { 1779 if (recog_data.operand_type[i] != OP_OUT) 1780 alt_cost += copy_cost (op, mode, classes[i], 1); 1781 1782 if (recog_data.operand_type[i] != OP_IN) 1783 alt_cost += copy_cost (op, mode, classes[i], 0); 1784 } 1785 1786 /* The only other way this alternative can be used is if this is a 1787 constant that could be placed into memory. */ 1788 1789 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i])) 1790 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1); 1791 else 1792 alt_fail = 1; 1793 } 1794 1795 if (alt_fail) 1796 continue; 1797 1798 /* Finally, update the costs with the information we've calculated 1799 about this alternative. */ 1800 1801 for (i = 0; i < n_ops; i++) 1802 if (REG_P (ops[i]) 1803 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1804 { 1805 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i]; 1806 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT); 1807 1808 pp->mem_cost = MIN (pp->mem_cost, 1809 (qq->mem_cost + alt_cost) * scale); 1810 1811 for (class = 0; class < N_REG_CLASSES; class++) 1812 pp->cost[class] = MIN (pp->cost[class], 1813 (qq->cost[class] + alt_cost) * scale); 1814 } 1815 } 1816 1817 /* If this insn is a single set copying operand 1 to operand 0 1818 and one operand is a pseudo with the other a hard reg or a pseudo 1819 that prefers a register that is in its own register class then 1820 we may want to adjust the cost of that register class to -1. 1821 1822 Avoid the adjustment if the source does not die to avoid stressing of 1823 register allocator by preferrencing two colliding registers into single 1824 class. 1825 1826 Also avoid the adjustment if a copy between registers of the class 1827 is expensive (ten times the cost of a default copy is considered 1828 arbitrarily expensive). This avoids losing when the preferred class 1829 is very expensive as the source of a copy instruction. */ 1830 1831 if ((set = single_set (insn)) != 0 1832 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set) 1833 && REG_P (ops[0]) && REG_P (ops[1]) 1834 && find_regno_note (insn, REG_DEAD, REGNO (ops[1]))) 1835 for (i = 0; i <= 1; i++) 1836 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER) 1837 { 1838 unsigned int regno = REGNO (ops[!i]); 1839 enum machine_mode mode = GET_MODE (ops[!i]); 1840 int class; 1841 unsigned int nr; 1842 1843 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0) 1844 { 1845 enum reg_class pref = reg_pref[regno].prefclass; 1846 1847 if ((reg_class_size[(unsigned char) pref] 1848 == (unsigned) CLASS_MAX_NREGS (pref, mode)) 1849 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2) 1850 op_costs[i].cost[(unsigned char) pref] = -1; 1851 } 1852 else if (regno < FIRST_PSEUDO_REGISTER) 1853 for (class = 0; class < N_REG_CLASSES; class++) 1854 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1855 && reg_class_size[class] == (unsigned) CLASS_MAX_NREGS (class, mode)) 1856 { 1857 if (reg_class_size[class] == 1) 1858 op_costs[i].cost[class] = -1; 1859 else 1860 { 1861 for (nr = 0; nr < (unsigned) hard_regno_nregs[regno][mode]; nr++) 1862 { 1863 if (! TEST_HARD_REG_BIT (reg_class_contents[class], 1864 regno + nr)) 1865 break; 1866 } 1867 1868 if (nr == (unsigned) hard_regno_nregs[regno][mode]) 1869 op_costs[i].cost[class] = -1; 1870 } 1871 } 1872 } 1873} 1874 1875/* Compute the cost of loading X into (if TO_P is nonzero) or from (if 1876 TO_P is zero) a register of class CLASS in mode MODE. 1877 1878 X must not be a pseudo. */ 1879 1880static int 1881copy_cost (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED, 1882 enum reg_class class, int to_p ATTRIBUTE_UNUSED) 1883{ 1884#ifdef HAVE_SECONDARY_RELOADS 1885 enum reg_class secondary_class = NO_REGS; 1886#endif 1887 1888 /* If X is a SCRATCH, there is actually nothing to move since we are 1889 assuming optimal allocation. */ 1890 1891 if (GET_CODE (x) == SCRATCH) 1892 return 0; 1893 1894 /* Get the class we will actually use for a reload. */ 1895 class = PREFERRED_RELOAD_CLASS (x, class); 1896 1897#ifdef HAVE_SECONDARY_RELOADS 1898 /* If we need a secondary reload (we assume here that we are using 1899 the secondary reload as an intermediate, not a scratch register), the 1900 cost is that to load the input into the intermediate register, then 1901 to copy them. We use a special value of TO_P to avoid recursion. */ 1902 1903#ifdef SECONDARY_INPUT_RELOAD_CLASS 1904 if (to_p == 1) 1905 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x); 1906#endif 1907 1908#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 1909 if (! to_p) 1910 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x); 1911#endif 1912 1913 if (secondary_class != NO_REGS) 1914 return (move_cost[mode][(int) secondary_class][(int) class] 1915 + copy_cost (x, mode, secondary_class, 2)); 1916#endif /* HAVE_SECONDARY_RELOADS */ 1917 1918 /* For memory, use the memory move cost, for (hard) registers, use the 1919 cost to move between the register classes, and use 2 for everything 1920 else (constants). */ 1921 1922 if (MEM_P (x) || class == NO_REGS) 1923 return MEMORY_MOVE_COST (mode, class, to_p); 1924 1925 else if (REG_P (x)) 1926 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class]; 1927 1928 else 1929 /* If this is a constant, we may eventually want to call rtx_cost here. */ 1930 return COSTS_N_INSNS (1); 1931} 1932 1933/* Record the pseudo registers we must reload into hard registers 1934 in a subexpression of a memory address, X. 1935 1936 CLASS is the class that the register needs to be in and is either 1937 BASE_REG_CLASS or INDEX_REG_CLASS. 1938 1939 SCALE is twice the amount to multiply the cost by (it is twice so we 1940 can represent half-cost adjustments). */ 1941 1942static void 1943record_address_regs (rtx x, enum reg_class class, int scale) 1944{ 1945 enum rtx_code code = GET_CODE (x); 1946 1947 switch (code) 1948 { 1949 case CONST_INT: 1950 case CONST: 1951 case CC0: 1952 case PC: 1953 case SYMBOL_REF: 1954 case LABEL_REF: 1955 return; 1956 1957 case PLUS: 1958 /* When we have an address that is a sum, 1959 we must determine whether registers are "base" or "index" regs. 1960 If there is a sum of two registers, we must choose one to be 1961 the "base". Luckily, we can use the REG_POINTER to make a good 1962 choice most of the time. We only need to do this on machines 1963 that can have two registers in an address and where the base 1964 and index register classes are different. 1965 1966 ??? This code used to set REGNO_POINTER_FLAG in some cases, but 1967 that seems bogus since it should only be set when we are sure 1968 the register is being used as a pointer. */ 1969 1970 { 1971 rtx arg0 = XEXP (x, 0); 1972 rtx arg1 = XEXP (x, 1); 1973 enum rtx_code code0 = GET_CODE (arg0); 1974 enum rtx_code code1 = GET_CODE (arg1); 1975 1976 /* Look inside subregs. */ 1977 if (code0 == SUBREG) 1978 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); 1979 if (code1 == SUBREG) 1980 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); 1981 1982 /* If this machine only allows one register per address, it must 1983 be in the first operand. */ 1984 1985 if (MAX_REGS_PER_ADDRESS == 1) 1986 record_address_regs (arg0, class, scale); 1987 1988 /* If index and base registers are the same on this machine, just 1989 record registers in any non-constant operands. We assume here, 1990 as well as in the tests below, that all addresses are in 1991 canonical form. */ 1992 1993 else if (INDEX_REG_CLASS == MODE_BASE_REG_CLASS (VOIDmode)) 1994 { 1995 record_address_regs (arg0, class, scale); 1996 if (! CONSTANT_P (arg1)) 1997 record_address_regs (arg1, class, scale); 1998 } 1999 2000 /* If the second operand is a constant integer, it doesn't change 2001 what class the first operand must be. */ 2002 2003 else if (code1 == CONST_INT || code1 == CONST_DOUBLE) 2004 record_address_regs (arg0, class, scale); 2005 2006 /* If the second operand is a symbolic constant, the first operand 2007 must be an index register. */ 2008 2009 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF) 2010 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2011 2012 /* If both operands are registers but one is already a hard register 2013 of index or reg-base class, give the other the class that the 2014 hard register is not. */ 2015 2016 else if (code0 == REG && code1 == REG 2017 && REGNO (arg0) < FIRST_PSEUDO_REGISTER 2018 && (REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode) 2019 || REG_OK_FOR_INDEX_P (arg0))) 2020 record_address_regs (arg1, 2021 REG_MODE_OK_FOR_REG_BASE_P (arg0, VOIDmode) 2022 ? INDEX_REG_CLASS 2023 : MODE_BASE_REG_REG_CLASS (VOIDmode), 2024 scale); 2025 else if (code0 == REG && code1 == REG 2026 && REGNO (arg1) < FIRST_PSEUDO_REGISTER 2027 && (REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode) 2028 || REG_OK_FOR_INDEX_P (arg1))) 2029 record_address_regs (arg0, 2030 REG_MODE_OK_FOR_REG_BASE_P (arg1, VOIDmode) 2031 ? INDEX_REG_CLASS 2032 : MODE_BASE_REG_REG_CLASS (VOIDmode), 2033 scale); 2034 2035 /* If one operand is known to be a pointer, it must be the base 2036 with the other operand the index. Likewise if the other operand 2037 is a MULT. */ 2038 2039 else if ((code0 == REG && REG_POINTER (arg0)) 2040 || code1 == MULT) 2041 { 2042 record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode), 2043 scale); 2044 record_address_regs (arg1, INDEX_REG_CLASS, scale); 2045 } 2046 else if ((code1 == REG && REG_POINTER (arg1)) 2047 || code0 == MULT) 2048 { 2049 record_address_regs (arg0, INDEX_REG_CLASS, scale); 2050 record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode), 2051 scale); 2052 } 2053 2054 /* Otherwise, count equal chances that each might be a base 2055 or index register. This case should be rare. */ 2056 2057 else 2058 { 2059 record_address_regs (arg0, MODE_BASE_REG_REG_CLASS (VOIDmode), 2060 scale / 2); 2061 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2); 2062 record_address_regs (arg1, MODE_BASE_REG_REG_CLASS (VOIDmode), 2063 scale / 2); 2064 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2); 2065 } 2066 } 2067 break; 2068 2069 /* Double the importance of a pseudo register that is incremented 2070 or decremented, since it would take two extra insns 2071 if it ends up in the wrong place. */ 2072 case POST_MODIFY: 2073 case PRE_MODIFY: 2074 record_address_regs (XEXP (x, 0), MODE_BASE_REG_CLASS (VOIDmode), 2075 2 * scale); 2076 if (REG_P (XEXP (XEXP (x, 1), 1))) 2077 record_address_regs (XEXP (XEXP (x, 1), 1), 2078 INDEX_REG_CLASS, 2 * scale); 2079 break; 2080 2081 case POST_INC: 2082 case PRE_INC: 2083 case POST_DEC: 2084 case PRE_DEC: 2085 /* Double the importance of a pseudo register that is incremented 2086 or decremented, since it would take two extra insns 2087 if it ends up in the wrong place. If the operand is a pseudo, 2088 show it is being used in an INC_DEC context. */ 2089 2090#ifdef FORBIDDEN_INC_DEC_CLASSES 2091 if (REG_P (XEXP (x, 0)) 2092 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER) 2093 in_inc_dec[REGNO (XEXP (x, 0))] = 1; 2094#endif 2095 2096 record_address_regs (XEXP (x, 0), class, 2 * scale); 2097 break; 2098 2099 case REG: 2100 { 2101 struct costs *pp = &costs[REGNO (x)]; 2102 int i; 2103 2104 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2; 2105 2106 for (i = 0; i < N_REG_CLASSES; i++) 2107 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2; 2108 } 2109 break; 2110 2111 default: 2112 { 2113 const char *fmt = GET_RTX_FORMAT (code); 2114 int i; 2115 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2116 if (fmt[i] == 'e') 2117 record_address_regs (XEXP (x, i), class, scale); 2118 } 2119 } 2120} 2121 2122#ifdef FORBIDDEN_INC_DEC_CLASSES 2123 2124/* Return 1 if REG is valid as an auto-increment memory reference 2125 to an object of MODE. */ 2126 2127static int 2128auto_inc_dec_reg_p (rtx reg, enum machine_mode mode) 2129{ 2130 if (HAVE_POST_INCREMENT 2131 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg))) 2132 return 1; 2133 2134 if (HAVE_POST_DECREMENT 2135 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg))) 2136 return 1; 2137 2138 if (HAVE_PRE_INCREMENT 2139 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg))) 2140 return 1; 2141 2142 if (HAVE_PRE_DECREMENT 2143 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg))) 2144 return 1; 2145 2146 return 0; 2147} 2148#endif 2149 2150static short *renumber; 2151static size_t regno_allocated; 2152static unsigned int reg_n_max; 2153 2154/* Allocate enough space to hold NUM_REGS registers for the tables used for 2155 reg_scan and flow_analysis that are indexed by the register number. If 2156 NEW_P is nonzero, initialize all of the registers, otherwise only 2157 initialize the new registers allocated. The same table is kept from 2158 function to function, only reallocating it when we need more room. If 2159 RENUMBER_P is nonzero, allocate the reg_renumber array also. */ 2160 2161void 2162allocate_reg_info (size_t num_regs, int new_p, int renumber_p) 2163{ 2164 size_t size_info; 2165 size_t size_renumber; 2166 size_t min = (new_p) ? 0 : reg_n_max; 2167 struct reg_info_data *reg_data; 2168 2169 if (num_regs > regno_allocated) 2170 { 2171 size_t old_allocated = regno_allocated; 2172 2173 regno_allocated = num_regs + (num_regs / 20); /* Add some slop space. */ 2174 size_renumber = regno_allocated * sizeof (short); 2175 2176 if (!reg_n_info) 2177 { 2178 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info"); 2179 renumber = xmalloc (size_renumber); 2180 reg_pref_buffer = xmalloc (regno_allocated 2181 * sizeof (struct reg_pref)); 2182 } 2183 else 2184 { 2185 VARRAY_GROW (reg_n_info, regno_allocated); 2186 2187 if (new_p) /* If we're zapping everything, no need to realloc. */ 2188 { 2189 free ((char *) renumber); 2190 free ((char *) reg_pref); 2191 renumber = xmalloc (size_renumber); 2192 reg_pref_buffer = xmalloc (regno_allocated 2193 * sizeof (struct reg_pref)); 2194 } 2195 2196 else 2197 { 2198 renumber = xrealloc (renumber, size_renumber); 2199 reg_pref_buffer = xrealloc (reg_pref_buffer, 2200 regno_allocated 2201 * sizeof (struct reg_pref)); 2202 } 2203 } 2204 2205 size_info = (regno_allocated - old_allocated) * sizeof (reg_info) 2206 + sizeof (struct reg_info_data) - sizeof (reg_info); 2207 reg_data = xcalloc (size_info, 1); 2208 reg_data->min_index = old_allocated; 2209 reg_data->max_index = regno_allocated - 1; 2210 reg_data->next = reg_info_head; 2211 reg_info_head = reg_data; 2212 } 2213 2214 reg_n_max = num_regs; 2215 if (min < num_regs) 2216 { 2217 /* Loop through each of the segments allocated for the actual 2218 reg_info pages, and set up the pointers, zero the pages, etc. */ 2219 for (reg_data = reg_info_head; 2220 reg_data && reg_data->max_index >= min; 2221 reg_data = reg_data->next) 2222 { 2223 size_t min_index = reg_data->min_index; 2224 size_t max_index = reg_data->max_index; 2225 size_t max = MIN (max_index, num_regs); 2226 size_t local_min = min - min_index; 2227 size_t i; 2228 2229 if (reg_data->min_index > num_regs) 2230 continue; 2231 2232 if (min < min_index) 2233 local_min = 0; 2234 if (!reg_data->used_p) /* page just allocated with calloc */ 2235 reg_data->used_p = 1; /* no need to zero */ 2236 else 2237 memset (®_data->data[local_min], 0, 2238 sizeof (reg_info) * (max - min_index - local_min + 1)); 2239 2240 for (i = min_index+local_min; i <= max; i++) 2241 { 2242 VARRAY_REG (reg_n_info, i) = ®_data->data[i-min_index]; 2243 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN; 2244 renumber[i] = -1; 2245 reg_pref_buffer[i].prefclass = (char) NO_REGS; 2246 reg_pref_buffer[i].altclass = (char) NO_REGS; 2247 } 2248 } 2249 } 2250 2251 /* If {pref,alt}class have already been allocated, update the pointers to 2252 the newly realloced ones. */ 2253 if (reg_pref) 2254 reg_pref = reg_pref_buffer; 2255 2256 if (renumber_p) 2257 reg_renumber = renumber; 2258} 2259 2260/* Free up the space allocated by allocate_reg_info. */ 2261void 2262free_reg_info (void) 2263{ 2264 if (reg_n_info) 2265 { 2266 struct reg_info_data *reg_data; 2267 struct reg_info_data *reg_next; 2268 2269 VARRAY_FREE (reg_n_info); 2270 for (reg_data = reg_info_head; reg_data; reg_data = reg_next) 2271 { 2272 reg_next = reg_data->next; 2273 free ((char *) reg_data); 2274 } 2275 2276 free (reg_pref_buffer); 2277 reg_pref_buffer = (struct reg_pref *) 0; 2278 reg_info_head = (struct reg_info_data *) 0; 2279 renumber = (short *) 0; 2280 } 2281 regno_allocated = 0; 2282 reg_n_max = 0; 2283} 2284 2285/* This is the `regscan' pass of the compiler, run just before cse 2286 and again just before loop. 2287 2288 It finds the first and last use of each pseudo-register 2289 and records them in the vectors regno_first_uid, regno_last_uid 2290 and counts the number of sets in the vector reg_n_sets. 2291 2292 REPEAT is nonzero the second time this is called. */ 2293 2294/* Maximum number of parallel sets and clobbers in any insn in this fn. 2295 Always at least 3, since the combiner could put that many together 2296 and we want this to remain correct for all the remaining passes. 2297 This corresponds to the maximum number of times note_stores will call 2298 a function for any insn. */ 2299 2300int max_parallel; 2301 2302/* Used as a temporary to record the largest number of registers in 2303 PARALLEL in a SET_DEST. This is added to max_parallel. */ 2304 2305static int max_set_parallel; 2306 2307void 2308reg_scan (rtx f, unsigned int nregs) 2309{ 2310 rtx insn; 2311 2312 timevar_push (TV_REG_SCAN); 2313 2314 allocate_reg_info (nregs, TRUE, FALSE); 2315 max_parallel = 3; 2316 max_set_parallel = 0; 2317 2318 for (insn = f; insn; insn = NEXT_INSN (insn)) 2319 if (INSN_P (insn)) 2320 { 2321 rtx pat = PATTERN (insn); 2322 if (GET_CODE (pat) == PARALLEL 2323 && XVECLEN (pat, 0) > max_parallel) 2324 max_parallel = XVECLEN (pat, 0); 2325 reg_scan_mark_refs (pat, insn, 0, 0); 2326 2327 if (REG_NOTES (insn)) 2328 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0); 2329 } 2330 2331 max_parallel += max_set_parallel; 2332 2333 timevar_pop (TV_REG_SCAN); 2334} 2335 2336/* Update 'regscan' information by looking at the insns 2337 from FIRST to LAST. Some new REGs have been created, 2338 and any REG with number greater than OLD_MAX_REGNO is 2339 such a REG. We only update information for those. */ 2340 2341void 2342reg_scan_update (rtx first, rtx last, unsigned int old_max_regno) 2343{ 2344 rtx insn; 2345 2346 allocate_reg_info (max_reg_num (), FALSE, FALSE); 2347 2348 for (insn = first; insn != last; insn = NEXT_INSN (insn)) 2349 if (INSN_P (insn)) 2350 { 2351 rtx pat = PATTERN (insn); 2352 if (GET_CODE (pat) == PARALLEL 2353 && XVECLEN (pat, 0) > max_parallel) 2354 max_parallel = XVECLEN (pat, 0); 2355 reg_scan_mark_refs (pat, insn, 0, old_max_regno); 2356 2357 if (REG_NOTES (insn)) 2358 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno); 2359 } 2360} 2361 2362/* X is the expression to scan. INSN is the insn it appears in. 2363 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. 2364 We should only record information for REGs with numbers 2365 greater than or equal to MIN_REGNO. */ 2366 2367static void 2368reg_scan_mark_refs (rtx x, rtx insn, int note_flag, unsigned int min_regno) 2369{ 2370 enum rtx_code code; 2371 rtx dest; 2372 rtx note; 2373 2374 if (!x) 2375 return; 2376 code = GET_CODE (x); 2377 switch (code) 2378 { 2379 case CONST: 2380 case CONST_INT: 2381 case CONST_DOUBLE: 2382 case CONST_VECTOR: 2383 case CC0: 2384 case PC: 2385 case SYMBOL_REF: 2386 case LABEL_REF: 2387 case ADDR_VEC: 2388 case ADDR_DIFF_VEC: 2389 return; 2390 2391 case REG: 2392 { 2393 unsigned int regno = REGNO (x); 2394 2395 if (regno >= min_regno) 2396 { 2397 if (!note_flag) 2398 REGNO_LAST_UID (regno) = INSN_UID (insn); 2399 if (REGNO_FIRST_UID (regno) == 0) 2400 REGNO_FIRST_UID (regno) = INSN_UID (insn); 2401 /* If we are called by reg_scan_update() (indicated by min_regno 2402 being set), we also need to update the reference count. */ 2403 if (min_regno) 2404 REG_N_REFS (regno)++; 2405 } 2406 } 2407 break; 2408 2409 case EXPR_LIST: 2410 if (XEXP (x, 0)) 2411 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno); 2412 if (XEXP (x, 1)) 2413 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2414 break; 2415 2416 case INSN_LIST: 2417 if (XEXP (x, 1)) 2418 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno); 2419 break; 2420 2421 case CLOBBER: 2422 { 2423 rtx reg = XEXP (x, 0); 2424 if (REG_P (reg) 2425 && REGNO (reg) >= min_regno) 2426 { 2427 REG_N_SETS (REGNO (reg))++; 2428 REG_N_REFS (REGNO (reg))++; 2429 } 2430 else if (MEM_P (reg)) 2431 reg_scan_mark_refs (XEXP (reg, 0), insn, note_flag, min_regno); 2432 } 2433 break; 2434 2435 case SET: 2436 /* Count a set of the destination if it is a register. */ 2437 for (dest = SET_DEST (x); 2438 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART 2439 || GET_CODE (dest) == ZERO_EXTEND; 2440 dest = XEXP (dest, 0)) 2441 ; 2442 2443 /* For a PARALLEL, record the number of things (less the usual one for a 2444 SET) that are set. */ 2445 if (GET_CODE (dest) == PARALLEL) 2446 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1); 2447 2448 if (REG_P (dest) 2449 && REGNO (dest) >= min_regno) 2450 { 2451 REG_N_SETS (REGNO (dest))++; 2452 REG_N_REFS (REGNO (dest))++; 2453 } 2454 2455 /* If this is setting a pseudo from another pseudo or the sum of a 2456 pseudo and a constant integer and the other pseudo is known to be 2457 a pointer, set the destination to be a pointer as well. 2458 2459 Likewise if it is setting the destination from an address or from a 2460 value equivalent to an address or to the sum of an address and 2461 something else. 2462 2463 But don't do any of this if the pseudo corresponds to a user 2464 variable since it should have already been set as a pointer based 2465 on the type. */ 2466 2467 if (REG_P (SET_DEST (x)) 2468 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER 2469 && REGNO (SET_DEST (x)) >= min_regno 2470 /* If the destination pseudo is set more than once, then other 2471 sets might not be to a pointer value (consider access to a 2472 union in two threads of control in the presence of global 2473 optimizations). So only set REG_POINTER on the destination 2474 pseudo if this is the only set of that pseudo. */ 2475 && REG_N_SETS (REGNO (SET_DEST (x))) == 1 2476 && ! REG_USERVAR_P (SET_DEST (x)) 2477 && ! REG_POINTER (SET_DEST (x)) 2478 && ((REG_P (SET_SRC (x)) 2479 && REG_POINTER (SET_SRC (x))) 2480 || ((GET_CODE (SET_SRC (x)) == PLUS 2481 || GET_CODE (SET_SRC (x)) == LO_SUM) 2482 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT 2483 && REG_P (XEXP (SET_SRC (x), 0)) 2484 && REG_POINTER (XEXP (SET_SRC (x), 0))) 2485 || GET_CODE (SET_SRC (x)) == CONST 2486 || GET_CODE (SET_SRC (x)) == SYMBOL_REF 2487 || GET_CODE (SET_SRC (x)) == LABEL_REF 2488 || (GET_CODE (SET_SRC (x)) == HIGH 2489 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST 2490 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF 2491 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF)) 2492 || ((GET_CODE (SET_SRC (x)) == PLUS 2493 || GET_CODE (SET_SRC (x)) == LO_SUM) 2494 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST 2495 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF 2496 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF)) 2497 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0 2498 && (GET_CODE (XEXP (note, 0)) == CONST 2499 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF 2500 || GET_CODE (XEXP (note, 0)) == LABEL_REF)))) 2501 REG_POINTER (SET_DEST (x)) = 1; 2502 2503 /* If this is setting a register from a register or from a simple 2504 conversion of a register, propagate REG_EXPR. */ 2505 if (REG_P (dest)) 2506 { 2507 rtx src = SET_SRC (x); 2508 2509 while (GET_CODE (src) == SIGN_EXTEND 2510 || GET_CODE (src) == ZERO_EXTEND 2511 || GET_CODE (src) == TRUNCATE 2512 || (GET_CODE (src) == SUBREG && subreg_lowpart_p (src))) 2513 src = XEXP (src, 0); 2514 2515 if (!REG_ATTRS (dest) && REG_P (src)) 2516 REG_ATTRS (dest) = REG_ATTRS (src); 2517 if (!REG_ATTRS (dest) && MEM_P (src)) 2518 set_reg_attrs_from_mem (dest, src); 2519 } 2520 2521 /* ... fall through ... */ 2522 2523 default: 2524 { 2525 const char *fmt = GET_RTX_FORMAT (code); 2526 int i; 2527 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2528 { 2529 if (fmt[i] == 'e') 2530 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno); 2531 else if (fmt[i] == 'E' && XVEC (x, i) != 0) 2532 { 2533 int j; 2534 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2535 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno); 2536 } 2537 } 2538 } 2539 } 2540} 2541 2542/* Return nonzero if C1 is a subset of C2, i.e., if every register in C1 2543 is also in C2. */ 2544 2545int 2546reg_class_subset_p (enum reg_class c1, enum reg_class c2) 2547{ 2548 if (c1 == c2) return 1; 2549 2550 if (c2 == ALL_REGS) 2551 win: 2552 return 1; 2553 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int) c1], 2554 reg_class_contents[(int) c2], 2555 win); 2556 return 0; 2557} 2558 2559/* Return nonzero if there is a register that is in both C1 and C2. */ 2560 2561int 2562reg_classes_intersect_p (enum reg_class c1, enum reg_class c2) 2563{ 2564 HARD_REG_SET c; 2565 2566 if (c1 == c2) return 1; 2567 2568 if (c1 == ALL_REGS || c2 == ALL_REGS) 2569 return 1; 2570 2571 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]); 2572 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]); 2573 2574 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose); 2575 return 1; 2576 2577 lose: 2578 return 0; 2579} 2580 2581#ifdef CANNOT_CHANGE_MODE_CLASS 2582 2583struct subregs_of_mode_node 2584{ 2585 unsigned int block; 2586 unsigned char modes[MAX_MACHINE_MODE]; 2587}; 2588 2589static htab_t subregs_of_mode; 2590 2591static hashval_t 2592som_hash (const void *x) 2593{ 2594 const struct subregs_of_mode_node *a = x; 2595 return a->block; 2596} 2597 2598static int 2599som_eq (const void *x, const void *y) 2600{ 2601 const struct subregs_of_mode_node *a = x; 2602 const struct subregs_of_mode_node *b = y; 2603 return a->block == b->block; 2604} 2605 2606void 2607init_subregs_of_mode (void) 2608{ 2609 if (subregs_of_mode) 2610 htab_empty (subregs_of_mode); 2611 else 2612 subregs_of_mode = htab_create (100, som_hash, som_eq, free); 2613} 2614 2615void 2616record_subregs_of_mode (rtx subreg) 2617{ 2618 struct subregs_of_mode_node dummy, *node; 2619 enum machine_mode mode; 2620 unsigned int regno; 2621 void **slot; 2622 2623 if (!REG_P (SUBREG_REG (subreg))) 2624 return; 2625 2626 regno = REGNO (SUBREG_REG (subreg)); 2627 mode = GET_MODE (subreg); 2628 2629 if (regno < FIRST_PSEUDO_REGISTER) 2630 return; 2631 2632 dummy.block = regno & -8; 2633 slot = htab_find_slot_with_hash (subregs_of_mode, &dummy, 2634 dummy.block, INSERT); 2635 node = *slot; 2636 if (node == NULL) 2637 { 2638 node = xcalloc (1, sizeof (*node)); 2639 node->block = regno & -8; 2640 *slot = node; 2641 } 2642 2643 node->modes[mode] |= 1 << (regno & 7); 2644} 2645 2646/* Set bits in *USED which correspond to registers which can't change 2647 their mode from FROM to any mode in which REGNO was encountered. */ 2648 2649void 2650cannot_change_mode_set_regs (HARD_REG_SET *used, enum machine_mode from, 2651 unsigned int regno) 2652{ 2653 struct subregs_of_mode_node dummy, *node; 2654 enum machine_mode to; 2655 unsigned char mask; 2656 unsigned int i; 2657 2658 dummy.block = regno & -8; 2659 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); 2660 if (node == NULL) 2661 return; 2662 2663 mask = 1 << (regno & 7); 2664 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) 2665 if (node->modes[to] & mask) 2666 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2667 if (!TEST_HARD_REG_BIT (*used, i) 2668 && REG_CANNOT_CHANGE_MODE_P (i, from, to)) 2669 SET_HARD_REG_BIT (*used, i); 2670} 2671 2672/* Return 1 if REGNO has had an invalid mode change in CLASS from FROM 2673 mode. */ 2674 2675bool 2676invalid_mode_change_p (unsigned int regno, enum reg_class class, 2677 enum machine_mode from) 2678{ 2679 struct subregs_of_mode_node dummy, *node; 2680 enum machine_mode to; 2681 unsigned char mask; 2682 2683 dummy.block = regno & -8; 2684 node = htab_find_with_hash (subregs_of_mode, &dummy, dummy.block); 2685 if (node == NULL) 2686 return false; 2687 2688 mask = 1 << (regno & 7); 2689 for (to = VOIDmode; to < NUM_MACHINE_MODES; to++) 2690 if (node->modes[to] & mask) 2691 if (CANNOT_CHANGE_MODE_CLASS (from, to, class)) 2692 return true; 2693 2694 return false; 2695} 2696#endif /* CANNOT_CHANGE_MODE_CLASS */ 2697 2698#include "gt-regclass.h" 2699