Searched refs:CSR_WRITE_4 (Results 1 - 25 of 47) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/arch/arm/xscale/
H A Dixp425_pci_space.c53 #define CSR_WRITE_4(x, v) *(volatile uint32_t *) \ macro
270 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
271 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
274 CSR_WRITE_4(PCI_ISR, ISR_PFE);
290 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
291 CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
294 CSR_WRITE_4(PCI_ISR, ISR_PFE);
307 CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
308 CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
311 CSR_WRITE_4(PCI_IS
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H A Dpxa2x0_mci.c152 #define CSR_WRITE_4(sc, reg, val) \ macro
155 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
157 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
174 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
185 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
359 CSR_WRITE_4(sc, MMC_SPI, 0);
360 CSR_WRITE_4(sc, MMC_RESTO, 0x7f);
361 CSR_WRITE_4(sc, MMC_I_MASK, sc->sc_imask);
512 CSR_WRITE_4(sc, MMC_CLKRT, sc->sc_clkrt);
513 CSR_WRITE_4(s
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H A Dpxa2x0_i2c.c408 #define CSR_WRITE_4(sc,r,v) bus_space_write_4(sc->sc_iot, sc->sc_ioh, r, v) macro
420 CSR_WRITE_4(sc, I2C_ICR, ICR_UR);
421 CSR_WRITE_4(sc, I2C_ISAR, 0);
422 CSR_WRITE_4(sc, I2C_ISR, ISR_ALL);
425 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr);
449 CSR_WRITE_4(sc, I2C_ISR, isr);
458 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_START);
467 CSR_WRITE_4(sc, I2C_ICR, sc->sc_icr | ICR_STOP);
483 CSR_WRITE_4(sc, I2C_IDBR, (addr << 1) | rd_req);
484 CSR_WRITE_4(s
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/netbsd-6-1-5-RELEASE/sys/arch/sandpoint/stand/altboot/
H A Dskg.c50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
228 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */
251 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON);
253 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON);
273 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET);
274 CSR_WRITE_4(l, SK_RXRB1_START, 0);
275 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0);
276 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0);
277 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff);
278 CSR_WRITE_4(
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H A Dkse.c48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
177 CSR_WRITE_4(l, TDLB, VTOPHYS(txd));
178 CSR_WRITE_4(l, RDLB, VTOPHYS(rxd));
179 CSR_WRITE_4(l, MDTXC, 07); /* stretch short, add CRC, Tx enable */
180 CSR_WRITE_4(l, MDRXC, 01); /* Rx enable */
181 CSR_WRITE_4(l, MDRSC, 01); /* start receiving */
199 CSR_WRITE_4(l, MDTSC, 01); /* start transmission */
241 CSR_WRITE_4(l, MDRSC, 01); /* restart receiving */
254 CSR_WRITE_4(l, MDRSC, 01); /* necessary? */
H A Drge.c51 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
204 CSR_WRITE_4(l, RGE_TCR, l->tcr);
205 CSR_WRITE_4(l, RGE_RCR, l->rcr);
206 CSR_WRITE_4(l, RGE_TNPDS, VTOPHYS(txd));
207 CSR_WRITE_4(l, RGE_RDSAR, VTOPHYS(rxd));
208 CSR_WRITE_4(l, RGE_TNPDS + 4, 0);
209 CSR_WRITE_4(l, RGE_RDSAR + 4, 0);
298 CSR_WRITE_4(l, RGE_PHYAR, v);
313 CSR_WRITE_4(l, RGE_PHYAR, v);
H A Dsiisata.c42 #define CSR_WRITE_4(r,v) out32rb(r,v) macro
157 CSR_WRITE_4(sc, val | 01); /* perform init */
159 CSR_WRITE_4(sc, val);
H A Dfxp.c93 #define CSR_WRITE_4(l, r, v) out32rb((l)->iobase+(r), (v)) macro
202 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
220 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
276 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cbp));
299 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(cb_ias));
320 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, VTOPHYS(rfa));
351 CSR_WRITE_4(l, FXP_CSR_SCB_GENERAL, VTOPHYS(txd));
517 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
H A Dpcn.c48 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
160 CSR_WRITE_4(l, PCN_RDP, 0);
313 CSR_WRITE_4(l, PCN_RAP, r);
320 CSR_WRITE_4(l, PCN_RAP, r);
321 CSR_WRITE_4(l, PCN_RDP, v);
327 CSR_WRITE_4(l, PCN_RAP, r);
334 CSR_WRITE_4(l, PCN_RAP, r);
335 CSR_WRITE_4(l, PCN_BDP, v);
H A Dstg.c45 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v)) macro
234 CSR_WRITE_4(l, STGE_TFDListPtrHi, 0);
235 CSR_WRITE_4(l, STGE_TFDListPtrLo, VTOPHYS(txd));
236 CSR_WRITE_4(l, STGE_RFDListPtrHi, 0);
237 CSR_WRITE_4(l, STGE_RFDListPtrLo, VTOPHYS(rxd));
239 CSR_WRITE_4(l, STGE_MACCtrl, 0); /* do IFSSelect(0) first */
272 CSR_WRITE_4(l, STGE_MACCtrl, macctl);
302 CSR_WRITE_4(l, STGE_DMACtrl, DMAC_TxDMAPollNow);
364 CSR_WRITE_4(l, STGE_AsicCtrl, reg | AC_GlobalReset | AC_RxReset |
/netbsd-6-1-5-RELEASE/sys/dev/pci/
H A Dif_et.c255 CSR_WRITE_4(sc, ET_PM,
379 CSR_WRITE_4(sc, ET_MII_CMD, 0);
383 CSR_WRITE_4(sc, ET_MII_ADDR, val);
386 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
410 CSR_WRITE_4(sc, ET_MII_CMD, 0);
422 CSR_WRITE_4(sc, ET_MII_CMD, 0);
426 CSR_WRITE_4(sc, ET_MII_ADDR, val);
429 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val0, ET_MII_CTRL_VALUE));
448 CSR_WRITE_4(sc, ET_MII_CMD, 0);
479 CSR_WRITE_4(s
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H A Dif_alc.c168 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
196 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
251 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
330 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
355 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
357 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
360 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
381 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
429 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
644 CSR_WRITE_4(s
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H A Dif_bge.c798 CSR_WRITE_4(sc, off, val);
807 CSR_WRITE_4(sc, off, val);
817 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
828 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
830 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
831 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
851 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
854 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
901 CSR_WRITE_4(sc, BGE_EE_ADDR,
906 CSR_WRITE_4(s
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H A Dif_ti.c361 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
411 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
430 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
450 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
452 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
468 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
471 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
475 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
533 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
1048 CSR_WRITE_4(s
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H A Dif_ipwreg.h328 #define CSR_WRITE_4(sc, reg, val) \ macro
339 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
344 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
349 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
350 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_DATA, (val)); \
354 CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)); \
H A Dif_age.c355 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
386 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
442 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
445 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
501 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
510 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
567 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
576 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
611 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
613 CSR_WRITE_4(s
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H A Dif_ale.c153 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
192 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
248 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
299 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
1085 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1161 CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1296 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1325 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
1585 CSR_WRITE_4(s
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H A Dif_iwireg.h552 #define CSR_WRITE_4(sc, reg, val) \ macro
563 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
568 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
573 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
574 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
578 CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
H A Dif_ipw.c144 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
151 CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
213 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1148 CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1231 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1251 CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1254 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1295 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1457 CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1548 CSR_WRITE_4(s
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H A Dif_bgevar.h96 #define CSR_WRITE_4(sc, reg, val) \ macro
103 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
105 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
H A Dif_iwi.c164 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr);
171 CSR_WRITE_4(sc, IWI_CSR_INDIRECT_ADDR, addr);
253 CSR_WRITE_4(sc, IWI_CSR_INTR_MASK, 0);
1196 CSR_WRITE_4(sc, IWI_CSR_RX_BASE + i * 4, data->map->dm_segs[0].ds_addr);
1349 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, (sc->cmdq.next + 1) % sc->cmdq.count);
1396 CSR_WRITE_4(sc, IWI_CSR_RX_WIDX, hw);
1444 CSR_WRITE_4(sc, IWI_CSR_INTR, r);
1513 CSR_WRITE_4(sc, IWI_CSR_CMD_WIDX, sc->cmdq.cur);
1695 CSR_WRITE_4(sc, txq->csr_widx, txq->cur);
1891 CSR_WRITE_4(s
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/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Drtl81x9.c538 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
539 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF);
540 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF);
545 CSR_WRITE_4(sc, RTK_MAR0, 0);
546 CSR_WRITE_4(sc, RTK_MAR4, 0);
572 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
581 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1]));
582 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0]));
584 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]);
585 CSR_WRITE_4(s
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H A Drtl8169.c202 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
227 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
1381 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1715 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1786 CSR_WRITE_4(sc, RTK_IDR0, reg);
1788 CSR_WRITE_4(sc, RTK_IDR4, reg);
1800 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
1802 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
1805 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
1807 CSR_WRITE_4(s
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/netbsd-6-1-5-RELEASE/sys/arch/i386/stand/lib/netif/
H A Di82557.c122 #define CSR_WRITE_4(reg, val) outl(iobase + (reg), val) macro
206 CSR_WRITE_4(FXP_CSR_SCB_GENERAL, 0);
265 CSR_WRITE_4(FXP_CSR_SCB_GENERAL, SNDBUF_PHYS);
321 CSR_WRITE_4(FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
358 CSR_WRITE_4(FXP_CSR_SCB_GENERAL, SNDBUF_PHYS);
389 CSR_WRITE_4(FXP_CSR_SCB_GENERAL, RECVBUF_PHYS);
H A D3c90xb.c85 #define CSR_WRITE_4(reg, val) outl(iobase + (reg), val) macro
210 CSR_WRITE_4(ELINK_DNLISTPTR, 0);
213 CSR_WRITE_4(ELINK_UPLISTPTR, RECVBUF_PHYS);
413 CSR_WRITE_4(ELINK_DNLISTPTR, SNDBUF_PHYS);

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