Lines Matching refs:CSR_WRITE_4
355 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
386 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
442 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
445 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
501 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
510 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
567 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
576 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
611 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
613 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
1164 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1598 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
1612 CSR_WRITE_4(sc, 0x12FC, 0x6500);
1613 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1651 CSR_WRITE_4(sc, AGE_PAR0,
1653 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
1657 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
1659 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
1661 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
1663 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
1665 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
1667 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
1670 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
1676 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
1680 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
1696 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
1703 CSR_WRITE_4(sc, AGE_HDPX_CFG,
1722 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
1735 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
1739 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
1753 CSR_WRITE_4(sc, 0x12FC, 0x6500);
1758 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1794 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
1799 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
1806 CSR_WRITE_4(sc, AGE_RXQ_CFG,
1816 CSR_WRITE_4(sc, AGE_TXQ_CFG,
1826 CSR_WRITE_4(sc, AGE_DMA_CFG,
1832 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
1839 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
1844 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
1845 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
1851 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1860 CSR_WRITE_4(sc, AGE_MAC_CFG,
1874 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
1875 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
1878 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
1918 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
1919 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
1922 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
1929 CSR_WRITE_4(sc, AGE_DMA_CFG,
1933 CSR_WRITE_4(sc, AGE_TXQ_CFG,
1935 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2077 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2083 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2104 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2110 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2271 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2313 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
2314 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
2315 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);