dev/pci/if_ale.c

153 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
192 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
248 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
299 		CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
308 		CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
1085 		CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1161 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1296 	CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
1325 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
1585 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1587 	CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
1632 	CSR_WRITE_4(sc, ALE_PAR0,
1634 	CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
1641 	CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1648 	CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
1649 	CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
1650 	CSR_WRITE_4(sc, ALE_TPD_CNT,
1655 	CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
1657 	CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
1661 	CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
1663 	CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
1665 	CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
1676 	CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
1679 	CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
1682 	CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
1689 	CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
1698 	CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
1706 	CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
1715 	CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
1718 	CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
1725 	CSR_WRITE_4(sc, ALE_HDPX_CFG,
1743 		CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
1753 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
1758 		CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
1766 		CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
1774 	CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
1775 	CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
1778 	CSR_WRITE_4(sc, ALE_RXQ_CFG,
1785 	CSR_WRITE_4(sc, ALE_DMA_CFG,
1800 	CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
1823 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1830 	CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
1831 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1832 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
1871 	CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
1872 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1877 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
1880 	CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
1883 	CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
1890 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
1914 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1982 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2024 	CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
2025 	CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
2026 	CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);