Lines Matching refs:CSR_WRITE_4
168 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
196 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
251 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
330 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
355 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
357 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
360 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
381 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
429 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
644 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
738 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
739 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
741 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
751 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1430 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
1510 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
1676 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
1710 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
1879 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2027 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2079 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
2083 CSR_WRITE_4(sc, ALC_PAR0,
2085 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2091 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2094 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2095 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2097 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2099 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2103 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2104 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2106 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2107 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2108 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2110 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2124 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
2128 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2130 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
2131 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
2132 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
2134 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
2137 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2139 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2140 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2144 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
2145 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
2146 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
2147 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
2148 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
2149 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
2150 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
2151 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
2155 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
2162 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
2172 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2177 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
2179 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
2181 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
2183 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
2190 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
2208 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
2211 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
2214 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
2220 CSR_WRITE_4(sc, ALC_HDPX_CFG,
2234 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH,
2245 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
2248 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
2264 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
2273 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
2278 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
2279 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
2287 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
2306 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
2332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2339 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
2340 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
2341 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
2380 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
2381 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
2388 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
2395 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
2432 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2461 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
2465 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
2478 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
2484 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
2545 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
2596 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2638 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
2639 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
2640 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);