dev/pci/if_ipw.c

144 	CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
151 	CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
213 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1148 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1231 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1251 	CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1254 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1295 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1457 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1548 	CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base);
1700 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1702 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER);
1711 	CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1725 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1737 	CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1742 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1757 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1820 	CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK |
1824 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1827 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1829 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1839 	CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) |
2171 	CSR_WRITE_4(sc, IPW_CSR_TX_BASE,  sc->tbd_map->dm_segs[0].ds_addr);
2172 	CSR_WRITE_4(sc, IPW_CSR_TX_SIZE,  IPW_NTBD);
2173 	CSR_WRITE_4(sc, IPW_CSR_TX_READ,  0);
2174 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
2176 	CSR_WRITE_4(sc, IPW_CSR_RX_BASE,  sc->rbd_map->dm_segs[0].ds_addr);
2177 	CSR_WRITE_4(sc, IPW_CSR_RX_SIZE,  IPW_NRBD);
2178 	CSR_WRITE_4(sc, IPW_CSR_RX_READ,  0);
2179 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
2181 	CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr);
2221 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET);
2241 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2251 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);