Searched refs:CSR_WRITE_2 (Results 1 - 25 of 42) sorted by relevance

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/netbsd-6-1-5-RELEASE/sys/arch/i386/stand/lib/netif/
H A D3c90xb.c84 #define CSR_WRITE_2(reg, val) outw(iobase + (reg), val) macro
88 #define GO_WINDOW(x) CSR_WRITE_2(ELINK_COMMAND, WINDOW_SELECT | x)
135 CSR_WRITE_2(ELINK_COMMAND, GLOBAL_RESET);
198 CSR_WRITE_2(ELINK_COMMAND, RX_RESET);
200 CSR_WRITE_2(ELINK_COMMAND, TX_RESET);
203 CSR_WRITE_2(ELINK_COMMAND, SET_INTR_MASK | 0); /* disable */
204 CSR_WRITE_2(ELINK_COMMAND, ACK_INTR | 0xff);
208 CSR_WRITE_2(ELINK_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST);
211 CSR_WRITE_2(ELINK_COMMAND, TX_ENABLE);
214 CSR_WRITE_2(ELINK_COMMAN
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H A Di82557.c121 #define CSR_WRITE_2(reg, val) outw(iobase + (reg), val) macro
441 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
451 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
452 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
455 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
467 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
468 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
471 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL, reg);
480 CSR_WRITE_2(FXP_CSR_EEPROMCONTROL,
486 CSR_WRITE_2(FXP_CSR_EEPROMCONTRO
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/netbsd-6-1-5-RELEASE/sys/dev/pcmcia/
H A Dif_wi_pcmcia.c445 CSR_WRITE_2(sc, WI_PARAM0, WI_AUX_KEY0);
446 CSR_WRITE_2(sc, WI_PARAM1, WI_AUX_KEY1);
447 CSR_WRITE_2(sc, WI_PARAM2, WI_AUX_KEY2);
448 CSR_WRITE_2(sc, WI_CNTL, WI_CNTL_AUX_ENA_CNTL);
452 CSR_WRITE_2(sc, WI_PARAM0, 0);
453 CSR_WRITE_2(sc, WI_PARAM1, 0);
454 CSR_WRITE_2(sc, WI_PARAM2, 0);
455 CSR_WRITE_2(sc, WI_COMMAND, WI_CMD_READEE);
461 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
463 CSR_WRITE_2(s
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/netbsd-6-1-5-RELEASE/sys/arch/sandpoint/stand/altboot/
H A Dfxp.c91 #define CSR_WRITE_2(l, r, v) out16rb((l)->iobase+(r), (v)) macro
418 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
420 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
423 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
433 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
444 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
446 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
453 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
456 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
470 CSR_WRITE_2(s
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H A Dskg.c48 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
220 CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET);
221 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET);
222 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_SET);
224 CSR_WRITE_2(l, SK_CSR, CSR_SW_UNRESET);
226 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_UNRESET);
227 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_CLEAR);
246 CSR_WRITE_2(l, YUKON_SA1 + i * 4,
322 CSR_WRITE_2(l, YUKON_GPCR, reg);
402 CSR_WRITE_2(
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H A Dstg.c43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
192 CSR_WRITE_2(l, STGE_EepromCtrl,
231 CSR_WRITE_2(l, STGE_IntEnable, 0);
232 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast |
238 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE);
244 CSR_WRITE_2(l, STGE_DebugCtrl,
246 CSR_WRITE_2(l, STGE_DebugCtrl,
248 CSR_WRITE_2(l, STGE_DebugCtrl,
H A Dvge.c49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
294 CSR_WRITE_2(l, VR_RDCSIZE, NRXDESC - 1);
295 CSR_WRITE_2(l, VR_RBRDU, NRXDESC - 1);
297 CSR_WRITE_2(l, VR_TDCSIZE, 0);
302 CSR_WRITE_2(l, VR_TDCSR, 01);
330 CSR_WRITE_2(l, VR_TDCSR, 04);
448 CSR_WRITE_2(l, VR_MIIDATA, data);
H A Dkse.c50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
151 CSR_WRITE_2(l, CIDR, 1);
264 CSR_WRITE_2(l, P1CR4, val);
H A Dnvt.c49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
232 CSR_WRITE_2(l, VR_ISR, ~0);
233 CSR_WRITE_2(l, VR_IEN, 0);
366 CSR_WRITE_2(l, VR_MIIDATA, data);
H A Drge.c49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v)) macro
203 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE);
210 CSR_WRITE_2(l, RGE_ISR, ~0);
211 CSR_WRITE_2(l, RGE_IMR, 0);
/netbsd-6-1-5-RELEASE/sys/dev/pci/
H A Dif_vte.c342 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
364 CSR_WRITE_2(sc, VTE_MMWD, val);
365 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
417 CSR_WRITE_2(sc, VTE_MRICR, val);
425 CSR_WRITE_2(sc, VTE_MTICR, val);
814 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
890 CSR_WRITE_2(sc, VTE_MCR0, mcr);
967 CSR_WRITE_2(sc, VTE_MIER, 0);
988 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1172 CSR_WRITE_2(s
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H A Dif_vtevar.h148 #define CSR_WRITE_2(_sc, reg, val) \ macro
H A Dif_ipwreg.h325 #define CSR_WRITE_2(sc, reg, val) \ macro
345 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
H A Dif_vge.c261 #define CSR_WRITE_2(sc, reg, val) \ macro
276 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
283 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
577 CSR_WRITE_2(sc, VGE_MIIDATA, data);
1383 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1754 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1844 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
1847 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
1848 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
1855 CSR_WRITE_2(s
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H A Dif_wi_pci.c301 CSR_WRITE_2(sc, WI_INT_EN, 0);
302 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
H A Dif_kse.c68 #define CSR_WRITE_2(sc, off, val) \ macro
411 CSR_WRITE_2(sc, CIDR, 1);
837 CSR_WRITE_2(sc, GRR, 1);
839 CSR_WRITE_2(sc, GRR, 0);
841 CSR_WRITE_2(sc, CIDR, 1);
1281 CSR_WRITE_2(sc, P1CR4, ctl);
1399 CSR_WRITE_2(sc, IACR, val);
1413 CSR_WRITE_2(sc, IACR, 0x1c00 + 0x100 + p);
1415 CSR_WRITE_2(sc, IACR, 0x1c00 + 0x100 + p * 3 + 1);
1432 CSR_WRITE_2(s
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/netbsd-6-1-5-RELEASE/sys/dev/ic/
H A Dan.c448 CSR_WRITE_2(sc, AN_INT_EN, 0);
449 CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
464 CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS));
507 CSR_WRITE_2(sc, AN_SW0, AN_MAGIC);
635 CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);
654 CSR_WRITE_2(sc, AN_INT_EN, 0);
1343 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
1367 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
1379 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX);
1389 CSR_WRITE_2(s
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H A Di82557.c608 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
610 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
650 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
661 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
663 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
670 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
673 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
698 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
711 CSR_WRITE_2(s
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H A Drtl81x9.c296 CSR_WRITE_2(sc, RTK_MII, 0);
494 CSR_WRITE_2(sc, rtk8139_reg, data);
963 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
964 CSR_WRITE_2(sc, RTK_COMMAND,
1070 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
1170 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1181 CSR_WRITE_2(sc, RTK_ISR, status);
1204 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1399 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1481 CSR_WRITE_2(s
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H A Danvar.h50 #define CSR_WRITE_2(sc, reg, val) \ macro
H A Dwivar.h232 #define CSR_WRITE_2(sc, reg, val) \ macro
254 #define CSR_WRITE_2(sc, reg, val) \ macro
H A Dbwi.c788 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1170 CSR_WRITE_2(sc, data_reg, v);
1183 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
1186 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
1230 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
1305 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1322 CSR_WRITE_2(sc, 0x60e, 0);
1323 CSR_WRITE_2(sc, 0x610, 0x8000);
1324 CSR_WRITE_2(sc, 0x604, 0);
1325 CSR_WRITE_2(s
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H A Dbwivar.h87 #define CSR_WRITE_2(sc, reg, val) \ macro
93 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
98 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
103 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Drtl8169.c359 CSR_WRITE_2(sc, re8139_reg, data);
465 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
1437 CSR_WRITE_2(sc, RTK_ISR, status);
1769 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1773 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1858 CSR_WRITE_2(sc, RTK_IMR, 0);
1860 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
1886 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
1995 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1996 CSR_WRITE_2(s
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/netbsd-6-1-5-RELEASE/sys/arch/evbarm/ixm1200/
H A Dnappi_nppb.c69 #define CSR_WRITE_2(sc, reg, val) \ macro

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