Lines Matching refs:CSR_WRITE_2
84 #define CSR_WRITE_2(reg, val) outw(iobase + (reg), val)
88 #define GO_WINDOW(x) CSR_WRITE_2(ELINK_COMMAND, WINDOW_SELECT | x)
135 CSR_WRITE_2(ELINK_COMMAND, GLOBAL_RESET);
198 CSR_WRITE_2(ELINK_COMMAND, RX_RESET);
200 CSR_WRITE_2(ELINK_COMMAND, TX_RESET);
203 CSR_WRITE_2(ELINK_COMMAND, SET_INTR_MASK | 0); /* disable */
204 CSR_WRITE_2(ELINK_COMMAND, ACK_INTR | 0xff);
208 CSR_WRITE_2(ELINK_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST);
211 CSR_WRITE_2(ELINK_COMMAND, TX_ENABLE);
214 CSR_WRITE_2(ELINK_COMMAND, RX_ENABLE);
215 CSR_WRITE_2(ELINK_COMMAND, ELINK_UPUNSTALL);
225 CSR_WRITE_2(ELINK_W3_MAC_CONTROL, 0);
231 CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, 0);
232 CSR_WRITE_2(ELINK_COMMAND, STOP_TRANSCEIVER);
237 CSR_WRITE_2(ELINK_W4_MEDIA_TYPE,
241 CSR_WRITE_2(ELINK_COMMAND, START_TRANSCEIVER);
245 CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, SQE_ENABLE);
249 CSR_WRITE_2(ELINK_W4_MEDIA_TYPE, LINKBEAT_ENABLE);
263 CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG, config0);
264 CSR_WRITE_2(ELINK_W3_INTERNAL_CONFIG + 2, config1);
389 CSR_WRITE_2(ELINK_COMMAND, RX_DISABLE);
390 CSR_WRITE_2(ELINK_COMMAND, TX_DISABLE);
391 CSR_WRITE_2(ELINK_COMMAND, STOP_TRANSCEIVER);
392 CSR_WRITE_2(ELINK_COMMAND, INTR_LATCH);
414 CSR_WRITE_2(ELINK_COMMAND, ELINK_DNUNSTALL);
446 CSR_WRITE_2(ELINK_COMMAND, ELINK_UPUNSTALL);