Lines Matching refs:CSR_WRITE_2
342 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
364 CSR_WRITE_2(sc, VTE_MMWD, val);
365 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
417 CSR_WRITE_2(sc, VTE_MRICR, val);
425 CSR_WRITE_2(sc, VTE_MTICR, val);
814 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
890 CSR_WRITE_2(sc, VTE_MCR0, mcr);
967 CSR_WRITE_2(sc, VTE_MIER, 0);
988 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1172 CSR_WRITE_2(sc, VTE_MRDCR, prog |
1203 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1216 CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1217 CSR_WRITE_2(sc, VTE_MACSM, 0);
1267 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1268 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1269 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1274 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1275 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1280 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1281 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1288 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1301 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1304 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1315 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1322 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1329 CSR_WRITE_2(sc, VTE_MRICR, 0);
1330 CSR_WRITE_2(sc, VTE_MTICR, 0);
1333 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1338 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1339 CSR_WRITE_2(sc, VTE_MISR, 0);
1382 CSR_WRITE_2(sc, VTE_MIER, 0);
1383 CSR_WRITE_2(sc, VTE_MECIER, 0);
1439 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1464 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1633 CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
1634 CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
1635 CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
1636 CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
1640 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
1642 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
1644 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
1648 CSR_WRITE_2(sc, VTE_MCR0, mcr);