dev/ic/bwi.c

788 		CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1170 	CSR_WRITE_2(sc, data_reg, v);
1183 		CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
1186 		CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
1230 	CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
1305 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1322 		CSR_WRITE_2(sc, 0x60e, 0);
1323 		CSR_WRITE_2(sc, 0x610, 0x8000);
1324 		CSR_WRITE_2(sc, 0x604, 0);
1325 		CSR_WRITE_2(sc, 0x606, 0x200);
1349 	CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);
1398 	CSR_WRITE_2(sc, 0x612, 0x50);	/* Force Pre-TBTT to 80? */
1434 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1672 	CSR_WRITE_2(sc, 0x568, 0);
1673 	CSR_WRITE_2(sc, 0x7c0, 0);
1674 	CSR_WRITE_2(sc, 0x50c, val_50c);
1675 	CSR_WRITE_2(sc, 0x508, 0);
1676 	CSR_WRITE_2(sc, 0x50a, 0);
1677 	CSR_WRITE_2(sc, 0x54c, 0);
1678 	CSR_WRITE_2(sc, 0x56a, 0x14);
1679 	CSR_WRITE_2(sc, 0x568, 0x826);
1680 	CSR_WRITE_2(sc, 0x500, 0);
1681 	CSR_WRITE_2(sc, 0x502, 0x30);
2177 			CSR_WRITE_2(sc, ofs, val16);
2279 	CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);
2515 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
2586 	CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,
2943 	CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
2944 	CSR_WRITE_2(sc, BWI_PHY_DATA, data);
2953 	CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
3248 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
3258 	CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
3295 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
3342 		CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
3365 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
3373 		CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
3524 		CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
3531 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
3544 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
3864 	CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
3865 	CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
3883 	CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
3914 		CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
3918 		CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
4017 	CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
4242 		CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
4244 		CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
4246 	CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
4447 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
4484 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
4640 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
4642 		CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
4649 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
4956 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
4985 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
5033 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
5047 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5348 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
5362 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
5364 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
5388 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5396 		CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
5723 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5724 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
5725 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
6272 		CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
6349 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
6647 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
6693 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
6714 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
8386 	CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
8394 		CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);