Searched refs:VReg (Results 1 - 21 of 21) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DLiveIntervalUnion.h120 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument
121 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
136 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument
137 assert(VReg && LIU && "Invalid arguments");
138 if (UserTag == UTag && VirtReg == VReg &&
145 VirtReg = VReg;
163 bool isSeenInterference(LiveInterval *VReg) const;
H A DLiveIntervalUnion.cpp151 LiveInterval *VReg = LiveUnionI.value(); local
152 if (VReg != RecentReg && !isSeenInterference(VReg)) {
153 RecentReg = VReg;
154 InterferingVRegs.push_back(VReg);
H A DMachineFunction.cpp409 unsigned VReg = MRI.getLiveInVirtReg(PReg); local
410 if (VReg) {
411 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
412 return VReg;
414 VReg = MRI.createVirtualRegister(RC);
415 MRI.addLiveIn(PReg, VReg);
416 return VReg;
H A DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
38 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
40 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
H A DMachineRegisterInfo.cpp250 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
252 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
254 if (I->second == VReg)
H A DTailDuplication.cpp231 unsigned VReg = SSAUpdateVRs[i]; local
232 SSAUpdate.Initialize(VReg);
236 MachineInstr *DefMI = MRI->getVRegDef(VReg);
240 SSAUpdate.AddAvailableValue(DefBB, VReg);
245 SSAUpdateVals.find(VReg);
253 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
H A DRegAllocFast.cpp169 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, unsigned PhysReg);
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp271 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local
274 if (!VReg) {
276 VReg = MRI->createVirtualRegister(RC);
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
280 return VReg;
302 unsigned VReg = getVR(Op, VRBaseMap); local
303 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
311 // shrink VReg's register class within reason. For example, if VReg == GR32
312 // and II requires a GR32_NOSP, just constrain VReg t
[all...]
H A DInstrEmitter.h80 /// ConstrainForSubReg - Try to constrain VReg to a register class that
83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb1RegisterInfo.cpp599 unsigned VReg = 0;
697 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
702 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
705 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
709 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
712 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
H A DARMISelLowering.cpp2578 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); local
2579 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1905 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); local
1906 if (!VReg)
1907 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1924 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); local
1925 if (!VReg)
1926 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1928 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2098 unsigned VReg; local
2100 VReg
2123 unsigned VReg; local
2159 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); local
2173 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local
2208 unsigned VReg; local
2231 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); local
2306 unsigned VReg; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcISelLowering.cpp211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local
212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
213 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local
324 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
325 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DMachineRegisterInfo.h482 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
484 unsigned getLiveInPhysReg(unsigned VReg) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUISelLowering.cpp638 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); local
649 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
650 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
833 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); local
844 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
845 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
1187 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); local
1188 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1189 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1235 unsigned VReg local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp848 unsigned VReg = local
850 RegInfo.addLiveIn(VA.getLocReg(), VReg);
851 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
853 unsigned VReg = local
855 RegInfo.addLiveIn(VA.getLocReg(), VReg);
856 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreISelLowering.cpp1130 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local
1131 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1132 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1180 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local
1181 RegInfo.addLiveIn(ArgRegs[i], VReg);
1182 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp338 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); local
339 RegInfo.addLiveIn(VA.getLocReg(), VReg);
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsISelLowering.cpp888 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); local
889 MF.getRegInfo().addLiveIn(PReg, VReg);
890 return VReg;
3230 unsigned VReg = AddLiveIn(MF, *Reg, &Mips::CPU64RegsRegClass); local
3233 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(VReg, MVT::i64),
/macosx-10.9.5/JavaScriptCore-7537.78.1/jit/
H A DJIT.h604 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86ISelLowering.cpp2055 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], local
2057 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2082 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], local
2084 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);

Completed in 508 milliseconds