/macosx-10.9.5/cctools-845/otool/ |
H A D | ppc_disasm.c | 48 #define VA(x) (((x) >> 16) & 0x1f) macro 1811 VA(opcode), VB(opcode)); 1815 VA(opcode), VB(opcode)); 1819 VA(opcode), VB(opcode)); 1823 VA(opcode), VB(opcode)); 1827 VA(opcode), VB(opcode)); 1831 VA(opcode), VB(opcode)); 1835 VA(opcode), VB(opcode)); 1839 VA(opcode), VB(opcode)); 1843 VA(opcod [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 110 CCValAssign &VA = RVLocs[i]; local 111 assert(VA.isRegLoc() && "Can only return in registers!"); 113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 169 CCValAssign &VA = ArgLocs[i]; local 182 if (VA.isRegLoc()) { 183 if (VA.needsCustom()) { 184 assert(VA.getLocVT() == MVT::f64); 186 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 212 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 214 if (VA 411 CCValAssign &VA = ArgLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 727 CCValAssign &VA = ArgLocs[i]; local 728 MVT RegVT = VA.getLocVT(); 732 switch (VA.getLocInfo()) { 748 if (VA.isRegLoc()) { 749 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 752 assert(VA.isMemLoc()); 760 unsigned ArgSize = VA.getValVT().getSizeInBits()/8; 761 unsigned StackLoc = VA.getLocMemOffset() + 4; 899 CCValAssign &VA = ArgLocs[i]; local 902 if (VA 1042 CCValAssign &VA = RVLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 324 CCValAssign &VA = ArgLocs[i]; local 325 if (VA.isRegLoc()) { 327 EVT RegVT = VA.getLocVT(); 339 RegInfo.addLiveIn(VA.getLocReg(), VReg); 345 if (VA.getLocInfo() == CCValAssign::SExt) 347 DAG.getValueType(VA.getValVT())); 348 else if (VA.getLocInfo() == CCValAssign::ZExt) 350 DAG.getValueType(VA.getValVT())); 352 if (VA.getLocInfo() != CCValAssign::Full) 353 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA 415 CCValAssign &VA = RVLocs[i]; local 468 CCValAssign &VA = ArgLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86FastISel.cpp | 761 CCValAssign &VA = ValLocs[0]; 764 if (VA.getLocInfo() != CCValAssign::Full) 767 if (!VA.isRegLoc()) 772 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 775 unsigned SrcReg = Reg + VA.getValNo(); 777 EVT DstVT = VA.getValVT(); 801 unsigned DstReg = VA.getLocReg(); 810 MRI.addLiveOut(VA.getLocReg()); 1722 CCValAssign &VA local [all...] |
H A D | X86ISelLowering.cpp | 1522 CCValAssign &VA = RVLocs[i]; local 1523 assert(VA.isRegLoc() && "Can only return in registers!"); 1528 if (VA.getLocInfo() == CCValAssign::SExt) 1529 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); 1530 else if (VA.getLocInfo() == CCValAssign::ZExt) 1531 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); 1532 else if (VA.getLocInfo() == CCValAssign::AExt) 1533 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); 1534 else if (VA.getLocInfo() == CCValAssign::BCvt) 1535 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA 1679 CCValAssign &VA = RVLocs[i]; local 1809 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument 1890 CCValAssign &VA = ArgLocs[i]; local 2125 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 2272 CCValAssign &VA = ArgLocs[i]; local 2402 CCValAssign &VA = ArgLocs[i]; local 2807 CCValAssign &VA = RVLocs[i]; local 2870 CCValAssign &VA = ArgLocs[i]; local 2893 CCValAssign &VA = ArgLocs[i]; local [all...] |
H A D | X86ISelLowering.h | 734 const CCValAssign &VA, MachineFrameInfo *MFI, 738 const CCValAssign &VA,
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/macosx-10.9.5/cxxfilt-11/cxxfilt/opcodes/ |
H A D | ppc-opc.c | 510 /* The VA field in a VA, VX or VXR form instruction. */ 511 #define VA UI + 1 515 /* The VB field in a VA, VX or VXR form instruction. */ 516 #define VB VA + 1 520 /* The VC field in a VA form instruction. */ 525 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 539 /* The SHB field in a VA form instruction. */ 1660 /* An VA form instruction. */ 1663 /* The mask for an VA for 509 #define VA macro [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 318 CCValAssign &VA = RVLocs[i]; local 320 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 425 CCValAssign &VA = ArgLocs[i]; local 426 if (VA.isMemLoc()) { 449 CCValAssign &VA = ArgLocs[i]; local 454 switch (VA.getLocInfo()) { 461 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 464 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 467 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 471 if (VA 834 CCValAssign &VA = ArgLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 1907 CCValAssign &VA = ArgLocs[i]; local 1908 MVT ArgVT = ArgVTs[VA.getValNo()]; 1915 if (VA.isRegLoc() && !VA.needsCustom()) { 1917 } else if (VA.needsCustom()) { 1919 if (VA.getLocVT() != MVT::f64 || 1921 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1957 CCValAssign &VA = ArgLocs[i]; local 1958 unsigned Arg = ArgRegs[VA.getValNo()]; 1959 MVT ArgVT = ArgVTs[VA [all...] |
H A D | ARMISelLowering.h | 410 CCValAssign &VA, CCValAssign &NextVA, 414 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 422 const CCValAssign &VA,
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H A D | ARMISelLowering.cpp | 1196 CCValAssign VA = RVLocs[i]; local 1199 if (VA.needsCustom()) { 1201 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1205 VA = RVLocs[++i]; // skip ahead to next loc 1206 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1212 if (VA.getLocVT() == MVT::v2f64) { 1217 VA = RVLocs[++i]; // skip ahead to next loc 1218 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1221 VA = RVLocs[++i]; // skip ahead to next loc 1222 Hi = DAG.getCopyFromReg(Chain, dl, VA 1252 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument 1265 PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, SDValue Chain, SDValue &Arg, RegsToPassVector &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, SDValue &StackPtr, SmallVector<SDValue, 8> &MemOpChains, ISD::ArgFlagsTy Flags) const argument 1357 CCValAssign &VA = ArgLocs[i]; local 1831 CCValAssign &VA = ArgLocs[i]; local 1896 CCValAssign &VA = RVLocs[i]; local 2477 GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, DebugLoc dl) const argument 2624 CCValAssign &VA = ArgLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 941 CCValAssign &VA = ArgLocs[i]; local 945 switch (VA.getLocInfo()) { 949 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 952 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 955 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 961 if (VA.isRegLoc()) { 962 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 964 assert(VA.isMemLoc()); 966 int Offset = VA.getLocMemOffset(); 1115 CCValAssign &VA local 1246 CCValAssign &VA = RVLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2694 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2696 unsigned LocMemOffset = VA.getLocMemOffset(); 2785 const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, 2789 bool IsRegLoc = VA.isRegLoc(); 2795 LocMemOffset = VA.getLocMemOffset(); 2798 VA.getLocReg()); 2938 CCValAssign &VA = ArgLocs[i]; local 2939 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); 2948 MFI, DAG, Arg, VA, Flag 2690 WriteByValArg(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MVT PtrType, bool isLittle) argument 2781 PassByValArg64(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, EVT PtrTy, bool isLittle) argument 3178 ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, unsigned NumWords, SDValue FIN, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, const Argument *FuncArg) argument 3205 CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MachineFrameInfo *MFI, bool IsRegLoc, SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, EVT PtrTy, const Argument *FuncArg) argument 3278 CCValAssign &VA = ArgLocs[i]; local 3471 CCValAssign &VA = RVLocs[i]; local [all...] |
/macosx-10.9.5/xnu-2422.115.4/osfmk/i386/ |
H A D | pmap.h | 692 #define pmap_kernel_va(VA) \ 693 ((((vm_offset_t) (VA)) >= vm_min_kernel_address) && \ 694 (((vm_offset_t) (VA)) <= vm_max_kernel_address))
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/macosx-10.9.5/ICU-511.35/icuSources/ |
H A D | runConfigureICU | 50 Linux/VA Use the IBM Visual Age compiler on Power PC Linux 225 Linux/VA)
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 1787 CCValAssign &VA = ArgLocs[i]; local 1790 if (VA.isRegLoc()) { 1792 EVT ValVT = VA.getValVT(); 1815 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1821 assert(VA.isMemLoc()); 1823 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8; 1824 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), 1829 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2853 CCValAssign &VA = RVLocs[i]; local 2854 EVT VT = VA 3116 CCValAssign &VA = ArgLocs[i]; local 3681 CCValAssign &VA = RVLocs[i]; local [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 1147 CCValAssign &VA = ArgLocs[ArgNo]; local 1149 if (VA.isRegLoc()) { 1188 RegInfo.addLiveIn(VA.getLocReg(), VReg); 1317 CCValAssign &VA = ArgLocs[ArgRegIdx]; local 1340 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1457 CCValAssign VA = RVLocs[i]; local 1459 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1492 CCValAssign &VA = RVLocs[i]; local 1493 assert(VA [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Transforms/InstCombine/ |
H A D | InstCombinePHI.cpp | 880 Value *VA = PN.getIncomingValue(i); local 886 PN.setIncomingValue(j, VA);
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/macosx-10.9.5/misc_cmds-32/calendar/calendars/ |
H A D | calendar.birthday | 30 01/21 Thomas Jonathan "Stonewall" Jackson born in Clarksburg, VA, 1824
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/macosx-10.9.5/vim-53/runtime/keymap/ |
H A D | kana.vim | 605 VA ������
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/macosx-10.9.5/vim-53/runtime/ftplugin/ |
H A D | ocaml.vim | 9 " 2008 Jul 17 - Bugfix related to fnameescape (VA) 11 " needed anymore (VA)
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/macosx-10.9.5/OpenLDAP-491.1/OpenLDAP/libraries/liblunicode/ucdata/ |
H A D | MUTTUCData.txt | 260 E935;DEVANAGARI HALF LETTER VA;Lo;0;L;;;;;N;;;;;
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/macosx-10.9.5/CPANInternal-140/Crypt-SSLeay/certs/ |
H A D | ca-bundle.crt | 3414 ValiCert Class 1 VA 3470 ValiCert Class 2 VA 3526 ValiCert Class 3 VA
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/macosx-10.9.5/CPANInternal-140/Crypt-SSLeay-0.64/certs/ |
H A D | ca-bundle.crt | 3414 ValiCert Class 1 VA 3470 ValiCert Class 2 VA 3526 ValiCert Class 3 VA
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