Searched refs:DAG (Results 1 - 25 of 79) sorted by relevance

1234

/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp52 SelectionDAG &DAG; member in class:__anon10198::SelectionDAGLegalize
63 explicit SelectionDAGLegalize(SelectionDAG &DAG);
156 DAG.RemoveDeadNode(N);
162 DAG.ReplaceAllUsesWith(Old, New);
166 DAG.ReplaceAllUsesWith(Old, New);
170 DAG.ReplaceAllUsesWith(Old, New);
191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
211 DAG(dag) {
215 DAG
297 ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, const TargetLowering &TLI, SelectionDAGLegalize *DAGLegalize) argument
419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, const TargetLowering &TLI, SDValue &ValResult, SDValue &ChainResult) argument
724 DAG, TLI, this); local
829 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); local
[all...]
H A DLegalizeIntegerTypes.cpp36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
47 N->dump(&DAG); dbgs() << "\n";
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG
[all...]
H A DLegalizeVectorTypes.cpp35 N->dump(&DAG);
43 N->dump(&DAG);
131 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
139 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
151 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
161 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
168 return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
169 Op0, DAG.getValueType(NewVT),
170 DAG.getValueType(Op0.getValueType()),
177 return DAG
2276 FindMemType(SelectionDAG& DAG, const TargetLowering &TLI, unsigned Width, EVT WidenVT, unsigned Align = 0, unsigned WidenEx = 0) argument
2329 BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy, SmallVector<SDValue, 16>& LdOps, unsigned Start, unsigned End) argument
[all...]
H A DSelectionDAGBuilder.cpp1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
90 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
99 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, argument
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG
220 getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, const SDValue *Parts, unsigned NumParts, EVT PartVT, EVT ValueVT, const Value *V) argument
336 getCopyToParts(SelectionDAG &DAG, DebugLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, EVT PartVT, const Value *V, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) argument
467 getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, SDValue Val, SDValue *Parts, unsigned NumParts, EVT PartVT, const Value *V) argument
668 getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, DebugLoc dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
760 getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
811 AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, SelectionDAG &DAG, std::vector<SDValue> &Ops) const argument
3393 InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, SynchronizationScope Scope, bool Before, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI) argument
3659 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) argument
3673 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, DebugLoc dl) argument
3686 getF32Constant(SelectionDAG &DAG, unsigned Flt) argument
4387 ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG) argument
5194 Args, DAG, getCurDebugLoc()); local
5389 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG, local
5834 GetRegistersForValue(SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc DL, SDISelAsmOperandInfo &OpInfo) argument
6686 SelectionDAG &DAG = SDB->DAG; local
[all...]
H A DLegalizeTypesGeneric.cpp41 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
54 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
55 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
61 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
62 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
75 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
80 EVT InNVT = EVT::getVectorVT(*DAG
[all...]
H A DLegalizeVectorOps.cpp36 SelectionDAG& DAG; member in class:__anon10200::VectorLegalizer
82 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
92 DAG.AssignTopologicalOrder();
93 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
94 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
98 SDValue OldRoot = DAG.getRoot();
100 DAG.setRoot(LegalizedNodes[OldRoot]);
105 DAG.RemoveDeadNodes();
131 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0);
153 return LegalizeOp(TLI.LowerOperation(Result, DAG));
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp30 X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, argument
57 Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
66 CallLoweringInfo CLI(Chain, Type::getVoidTy(*DAG.getContext()),
70 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args,
71 DAG, dl);
113 Count = DAG.getIntPtrConstant(SizeVal);
119 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
123 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
128 Count = DAG
178 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
[all...]
H A DX86ISelLowering.h1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
11 // selection DAG.
29 // X86 Specific DAG Nodes
463 SelectionDAG &DAG) const;
503 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
509 SelectionDAG &DAG) const;
532 /// DAG node.
544 const SelectionDAG &DAG,
555 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
575 SelectionDAG &DAG) cons
[all...]
H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
11 // selection DAG.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
67 SelectionDAG &DAG, DebugLoc dl) {
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
77 return DAG.getUNDEF(ResultVT);
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG t
66 Extract128BitVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, DebugLoc dl) argument
100 Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal, SelectionDAG &DAG, DebugLoc dl) argument
130 Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) argument
1664 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1773 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, DebugLoc dl) argument
1809 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument
1850 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2125 LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const argument
2144 EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, SDValue Chain, bool IsTailCall, bool Is64Bit, int FPDiff, DebugLoc dl) const argument
2161 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, SDValue Chain, SDValue RetAddrFrIdx, bool Is64Bit, int FPDiff, DebugLoc dl) argument
2181 SelectionDAG &DAG = CLI.DAG; local
2957 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, SelectionDAG &DAG) argument
2968 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, unsigned TargetMask, SelectionDAG &DAG) argument
2982 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) argument
2995 getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue V1, SDValue V2, SelectionDAG &DAG) argument
3085 TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) argument
3521 Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
4144 CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
4292 getZeroVector(EVT VT, const X86Subtarget *Subtarget, SelectionDAG &DAG, DebugLoc dl) argument
4330 getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG, DebugLoc dl) argument
4365 getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4376 getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4388 getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) argument
4403 PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) argument
4421 getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) argument
4448 PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) argument
4490 getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
4585 getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG, unsigned Depth) argument
4652 getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems, bool ZerosFromLeft, SelectionDAG &DAG) argument
4698 isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
4731 isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
4764 isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, bool &isLeft, SDValue &ShVal, unsigned &ShAmt) argument
4780 LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument
4828 LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, unsigned NumNonZero, unsigned NumZero, SelectionDAG &DAG, const X86Subtarget* Subtarget, const TargetLowering &TLI) argument
4860 getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc dl) argument
4957 EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, DebugLoc &DL, SelectionDAG &DAG) argument
5576 LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) argument
5589 LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) argument
5599 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
5671 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
5921 LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, const X86TargetLowering &TLI) argument
6044 LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
6093 RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, DebugLoc dl) argument
6131 getVZextMovL(EVT VT, EVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget, DebugLoc dl) argument
6167 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
6281 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) argument
7190 LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) argument
7222 LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
7242 LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
7462 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags, bool LocalDynamic = false) argument
7493 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT) argument
7507 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT) argument
7513 LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, bool is64Bit) argument
7553 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, const EVT PtrVT, TLSModel::Model model, bool is64Bit, bool isPIC) argument
8086 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const argument
8354 LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) argument
8840 Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) argument
9038 isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) argument
9704 LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
9723 getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT, SDValue SrcOp, SDValue ShAmt, SelectionDAG &DAG) argument
9766 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) argument
10303 LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) argument
10403 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) argument
10626 LowerCTLZ(SDValue Op, SelectionDAG &DAG) argument
10660 LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) argument
10685 LowerCTTZ(SDValue Op, SelectionDAG &DAG) argument
10707 Lower256IntArith(SDValue Op, SelectionDAG &DAG) argument
10734 LowerADD(SDValue Op, SelectionDAG &DAG) argument
10741 LowerSUB(SDValue Op, SelectionDAG &DAG) argument
10748 LowerMUL(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
11024 LowerXALUO(SDValue Op, SelectionDAG &DAG) argument
11152 LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
11198 LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
11237 LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
11269 LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget, SelectionDAG &DAG) argument
11308 LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) argument
11324 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) argument
11349 LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) argument
11452 ReplaceATOMIC_LOAD(SDNode *Node, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) argument
11474 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, SelectionDAG &DAG, unsigned NewOp) argument
13478 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
13603 PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget* Subtarget) argument
13686 PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
13720 PerformTruncateCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
13844 XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument
13938 PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument
14025 PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
14427 PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
14604 PerformMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument
14664 PerformSHLCombine(SDNode *N, SelectionDAG &DAG) argument
14710 PerformShiftCombine(SDNode* N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
14837 CMPEQCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
14942 PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15018 PerformOrCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15166 performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) argument
15201 PerformXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15241 PerformLOADCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15359 PerformSTORECombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument
15711 PerformFADDCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument
15726 PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument
15742 PerformFORCombine(SDNode *N, SelectionDAG &DAG) argument
15757 PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) argument
15779 PerformFANDCombine(SDNode *N, SelectionDAG &DAG) argument
15791 PerformBTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI) argument
15810 PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) argument
15823 PerformSExtCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15878 PerformFMACombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget* Subtarget) argument
15918 PerformZExtCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
15987 PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) argument
16012 PerformSETCCCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
16041 PerformBrCondCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) argument
16062 PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) argument
16079 PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86TargetLowering *XTLI) argument
16110 PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) argument
16125 PerformADCCombine(SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI) argument
16153 OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) argument
16190 PerformAddCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument
16205 PerformSubCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) argument
16240 SelectionDAG &DAG = DCI.DAG; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonISelLowering.h1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===//
11 // selection DAG.
80 SelectionDAG& DAG) const;
85 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
95 DebugLoc dl, SelectionDAG &DAG,
97 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) cons
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
11 // selection DAG.
84 DebugLoc dl, SelectionDAG &DAG) const {
86 MachineFunction &MF = DAG.getMachineFunction();
92 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
93 DAG.getTarget(), RVLocs, *DAG.getContext());
113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
127 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
128 Chain = DAG
148 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
350 SelectionDAG &DAG = CLI.DAG; local
620 getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const argument
839 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
927 LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) argument
935 LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) argument
943 LowerBR_CC(SDValue Op, SelectionDAG &DAG) argument
975 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) argument
1006 LowerVASTART(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI) argument
1024 LowerVAARG(SDValue Op, SelectionDAG &DAG) argument
1058 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) argument
1077 getFLUSHW(SDValue Op, SelectionDAG &DAG) argument
1084 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) argument
1115 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) argument
[all...]
H A DSparcISelLowering.h1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
47 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
55 const SelectionDAG &DAG,
75 DebugLoc dl, SelectionDAG &DAG,
87 DebugLoc dl, SelectionDAG &DAG) const;
89 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
92 unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const;
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/
H A DSPUISelLowering.cpp1 //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===//
48 //! Expand a library call into an actual call DAG node
56 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG, argument
61 SDValue InChain = DAG.getEntryNode();
67 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
74 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
79 Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
86 Callee, Args, DAG, Op.getDebugLoc());
560 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { argument
563 EVT PtrVT = DAG
769 LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) argument
1011 LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) argument
1038 LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM) argument
1043 LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) argument
1067 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) argument
1095 LowerConstantFP(SDValue Op, SelectionDAG &DAG) argument
1117 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1255 isLSAAddress(SDValue Op, SelectionDAG &DAG) argument
1270 SelectionDAG &DAG = CLI.DAG; local
1535 get_vec_u18imm(SDNode *N, SelectionDAG &DAG, EVT ValueType) argument
1557 get_vec_i16imm(SDNode *N, SelectionDAG &DAG, EVT ValueType) argument
1580 get_vec_i10imm(SDNode *N, SelectionDAG &DAG, EVT ValueType) argument
1606 get_vec_i8imm(SDNode *N, SelectionDAG &DAG, EVT ValueType) argument
1625 get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, EVT ValueType) argument
1639 get_v4i32_imm(SDNode *N, SelectionDAG &DAG) argument
1648 get_v2i64_imm(SDNode *N, SelectionDAG &DAG) argument
1658 LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) argument
1733 LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, DebugLoc dl) argument
1837 LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) argument
1957 LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) argument
2003 LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) argument
2166 LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) argument
2201 LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, const TargetLowering &TLI) argument
2302 LowerByteImmed(SDValue Op, SelectionDAG &DAG) argument
2355 LowerCTPOP(SDValue Op, SelectionDAG &DAG) argument
2464 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, const SPUTargetLowering &TLI) argument
2490 LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, const SPUTargetLowering &TLI) argument
2515 LowerSETCC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
2647 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
2675 LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) argument
2718 LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) argument
2907 SelectionDAG &DAG = DCI.DAG; local
3167 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth ) const argument
[all...]
H A DSPUISelLowering.h1 //===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
11 // a selection DAG.
64 SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
66 SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
68 SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
70 SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
72 SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
74 SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
75 SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
77 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/
H A DMipsISelLowering.h1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
151 SelectionDAG &DAG) const;
154 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
160 SelectionDAG &DAG) const;
163 // DAG node.
180 DebugLoc dl, SelectionDAG &DAG,
184 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
185 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
186 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DMipsISelLowering.cpp1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
11 // selection DAG.
53 static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { argument
54 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
55 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
509 static SDValue PerformADDECombine(SDNode *N, SelectionDAG &DAG, argument
516 SelectMadd(N, &DAG))
522 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG &DAG, argument
529 SelectMsub(N, &DAG))
535 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG &DAG, argument
612 CreateFPCmp(SelectionDAG &DAG, const SDValue &Op) argument
634 CreateCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, DebugLoc DL) argument
644 PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
677 PerformANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
717 PerformORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
771 PerformADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget *Subtarget) argument
800 SelectionDAG &DAG = DCI.DAG; local
1940 LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasR2) argument
1985 LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool HasR2) argument
2041 LowerFABS32(SDValue Op, SelectionDAG &DAG, bool HasR2) argument
2070 LowerFABS64(SDValue Op, SelectionDAG &DAG, bool HasR2) argument
2180 LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument
2221 CreateLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD, SDValue Chain, SDValue Src, unsigned Offset) argument
2300 CreateStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD, SDValue Chain, unsigned Offset) argument
2365 LowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, bool HasI64In, bool HasI64Out) argument
2690 WriteByValArg(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MVT PtrType, bool isLittle) argument
2781 PassByValArg64(SDValue Chain, DebugLoc dl, SmallVector<std::pair<unsigned, SDValue>, 16> &RegsToPass, SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, EVT PtrTy, bool isLittle) argument
2873 SelectionDAG &DAG = CLI.DAG; local
3152 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3178 ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, unsigned NumWords, SDValue FIN, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, const Argument *FuncArg) argument
3205 CopyMips64ByValRegs(MachineFunction &MF, SDValue Chain, DebugLoc dl, std::vector<SDValue> &OutChains, SelectionDAG &DAG, const CCValAssign &VA, const ISD::ArgFlagsTy &Flags, MachineFrameInfo *MFI, bool IsRegLoc, SmallVectorImpl<SDValue> &InVals, MipsFunctionInfo *MipsFI, EVT PtrTy, const Argument *FuncArg) argument
3245 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/
H A DMSP430ISelLowering.h1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
11 // selection DAG.
79 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
82 /// DAG node.
85 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
86 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) cons
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/
H A DXCoreISelLowering.cpp1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
167 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
170 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
171 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
172 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
173 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
174 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
175 case ISD::LOAD: return LowerLOAD(Op, DAG);
176 case ISD::STORE: return LowerSTORE(Op, DAG);
177 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
252 BuildGetId(SelectionDAG &DAG, DebugLoc dl) argument
879 SelectionDAG &DAG = CLI.DAG; local
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1066 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1090 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1339 SelectionDAG &DAG = DCI.DAG; local
1527 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
H A DXCoreISelLowering.h1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
93 SelectionDAG &DAG) const;
96 // DAG node.
115 DebugLoc dl, SelectionDAG &DAG,
123 DebugLoc dl, SelectionDAG &DAG,
128 DebugLoc dl, SelectionDAG &DAG,
130 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
132 SelectionDAG &DAG) cons
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/
H A DPPCISelLowering.h1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
11 // selection DAG.
239 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
249 /// DAG node.
263 SelectionDAG &DAG) const;
269 SelectionDAG &DAG) const;
275 SelectionDAG &DAG) const;
280 SelectionDAG &DAG) const;
286 SelectionDAG &DAG) const;
292 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) cons
[all...]
H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
734 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { argument
777 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
780 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
784 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
787 return DAG.getTargetConstant(Val, MVT::i32);
838 return DAG.getTargetConstant(MaskVal, MVT::i32);
870 SelectionDAG &DAG) const {
890 DAG.ComputeMaskedBits(N.getOperand(0),
894 DAG
1198 LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) argument
1372 LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument
1528 LowerVASTART(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument
1712 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1729 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1947 LowerFormalArguments_Darwin_Or_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2333 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument
2400 CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, unsigned ParamSize) argument
2456 isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) argument
2483 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG, SDValue Chain, const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs, SmallVector<SDValue, 8> &MemOpChains, DebugLoc dl) argument
2501 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, bool isPPC64, bool isDarwinABI, DebugLoc dl) argument
2542 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) argument
2560 EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, bool isDarwinABI, DebugLoc dl) const argument
2594 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, DebugLoc dl) argument
2606 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVector<SDValue, 8> &MemOpChains, SmallVector<TailCallArgumentInfo, 8> &TailCallArguments, DebugLoc dl) argument
2631 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, bool isDarwinABI, SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) argument
2659 PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, const PPCSubtarget &PPCSubTarget) argument
2840 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2866 FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
2975 SelectionDAG &DAG = CLI.DAG; local
3001 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3214 LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3694 LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument
3776 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const argument
3872 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const argument
4115 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
4142 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, DebugLoc dl, EVT DestVT = MVT::Other) argument
4152 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, DebugLoc dl, EVT DestVT = MVT::Other) argument
4163 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, DebugLoc dl) argument
4344 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, DebugLoc dl) argument
5456 SelectionDAG &DAG = DCI.DAG; local
5714 computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp29 ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, argument
66 Loads[i] = DAG.getLoad(VT, dl, Chain,
67 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
68 DAG.getConstant(SrcOff, MVT::i32)),
74 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
79 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
80 DAG.getConstant(DstOff, MVT::i32)),
85 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
105 Loads[i] = DAG
143 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...]
H A DARMISelLowering.h1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
11 // selection DAG.
31 // ARM Specific DAG Nodes
253 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
259 SelectionDAG &DAG) const;
278 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
316 SelectionDAG &DAG) const;
324 SelectionDAG &DAG) const;
329 const SelectionDAG &DAG,
353 SelectionDAG &DAG) cons
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/
H A DNVPTXISelLowering.h1 //===-- NVPTXISelLowering.h - NVPTX DAG Lowering Interface ------*- C++ -*-===//
11 // selection DAG.
71 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
73 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
75 SelectionDAG &DAG) const;
105 SelectionDAG &DAG,
119 SelectionDAG &DAG) const;
123 SelectionDAG &DAG) const;
135 SDValue getExtSymb(SelectionDAG &DAG, const char *name, int idx, EVT =
137 SDValue getParamSymbol(SelectionDAG &DAG, in
[all...]
H A DNVPTXISelLowering.cpp10 // selection DAG.
275 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
278 Op = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
279 return DAG.getNode(NVPTXISD::Wrapper, dl, getPointerTy(), Op);
444 SelectionDAG &DAG = CLI.DAG; local
459 Chain = DAG.getCALLSEQ_START(Chain,
460 DAG.getIntPtrConstant(uniqueCallSite, true));
480 SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
482 DAG
865 getExtSymb(SelectionDAG &DAG, const char *inname, int idx, EVT v) const argument
875 getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const argument
880 getParamHelpSymbol(SelectionDAG &DAG, int idx) argument
913 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]

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