Searched refs:r2 (Results 1 - 25 of 43) sorted by relevance

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/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/commpage/
H A Dbigcopy_970.s116 neg r2,r12 // is destination cache-line-aligned?
121 andi. r2,r2,0x7F // #bytes to align
132 mr r5,r2 // number of bytes to copy
133 add rs,rs,r2 // then bump our parameters past initial copy
134 add rd,rd,r2
135 sub rc,rc,r2
149 srwi r2,rc,8 // get number of 256-byte chunks to xfer
156 mtctr r2 // set up loop count
158 cmpd cr7,r2,r
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H A Dmemset_g4.s63 mfspr r2,vrsave // we'll be using VRs
64 oris r0,r2,0x8000 // we use vr0
126 mtspr vrsave,r2 // restore caller's vrsave
H A Dmemset_g5.s79 mfspr r2,vrsave // we'll be using VRs
81 oris r0,r2,0x8000 // we use vr0
163 mtspr vrsave,r2 // restore caller's vrsave
H A Dbcopy_64.s44 * r2 = "w8"
59 #define rv r2
68 #define w8 r2
H A Dcommpage_asm.s117 ori r2,r11,MASK(MSR_FP) // turn FP on
118 mtmsr r2
/macosx-10.5.8/xnu-1228.15.4/iokit/Kernel/ppc/
H A DIOAsmSupport.s87 stw r2, FM_TOC_SAVE(r1)
89 lwz r2, 4(r9)
96 stw r2, FM_TOC_SAVE(r1)
100 lwz r2, 4(r9)
107 lwz r2, FM_TOC_SAVE(r1)
/macosx-10.5.8/xnu-1228.15.4/bsd/dev/ppc/
H A Dxsumas.s64 rlwinm r2,r3,0,0x3 ; get byte offset in word
66 cmpwi cr6,r2,0 ; is address word aligned?
69 subfic r0,r2,4 ; get #bytes in partial word
72 beq cr6,Laligned ; skip if already word aligned (r2==0 if aligned)
77 mtcrf 0x01,r2 ; move byte offset to cr7
80 slwi r8,r2,3 ; multiply byte offset by 8
85 and r2,r6,r7 ; zero fill on left
88 ; r2 = initial checksum
117 adde r2,r2,r
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H A Dmunge.s367 srawi r2,r6,31
369 stw r2,1*8+0(r4)
388 srawi r2,r7,31
390 stw r2,2*8+0(r4)
410 srawi r2,r8,31
413 stw r2,3*8+0(r4)
/macosx-10.5.8/xnu-1228.15.4/osfmk/kdp/ml/ppc/
H A Dkdp_asm.s47 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
49 ori r2,r2,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get FP and EE
51 andc r7,r7,r2 ; Clear FP, VEC, and EE
78 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector enable
80 ori r2,r2,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get FP and EE
82 andc r0,r0,r2 ; Clear FP, VEC, and EE
/macosx-10.5.8/xnu-1228.15.4/osfmk/ppc/
H A Datomic_switch.s113 mfsprg r2,1 ; Get the current activation
114 lwz r2,ACT_PER_PROC(r2) ; Get the per_proc block
123 stw r7,spcFlags(r2) ; Update per_proc version
130 xoris r2,r1,SYSCONTEXTSTATE ; Setup for System Context check
132 cmpwi r2,0 ; Check if state is System Context?
145 lwz r2,saver1+4(r4) ; Get current R1
150 stw r2,BEDA_SPRG1(r26) ; Save current R1
187 lwz r2,BTTD_INTERRUPT_VECTOR(r6) ; Get the interrupt vector
191 cmpwi r2,
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H A Dmovc.s164 lis r2,hi16(MASK(MSR_VEC)) ; Get the vector flag
166 ori r2,r2,lo16(MASK(MSR_FP)) ; Add the FP flag
171 andc r11,r11,r2 // Clear out vec and fp
172 ori r2,r2,lo16(MASK(MSR_EE)) // Get EE on also
173 andc r2,r11,r2 // Clear out EE as well
175 ori r2,r2,MAS
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H A Dsavearea_asm.s242 sldi r2,r8,12 ; r2 <-- phys address of page
244 mr r4,r2 ; Point to start of chain
262 std r2,SVfree(0) ; Queue in the new one
271 slwi r2,r8,12 ; r2 <-- phys address of page
273 mr r4,r2 ; Point to start of chain
291 stw r2,SVfree+4(0) ; Queue in the new one
301 mfsprg r2,1 ; (TEST/DEBUG)
302 mr. r2,r
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H A DAltiAssist.s77 stvxl v0,r10,r2 ; Save V0
78 stvxl v1,r11,r2 ; Save V1
85 lvxl v0,r10,r2 ; Restore V0
87 lvxl v1,r11,r2 ; Restore V1
H A Dbzero.s140 // r2 = temp
176 sub r2,r4,r0 // adjust length
178 srwi. r8,r2,5 // get #32-byte chunks
181 rlwinm r4,r2,0,27,31 // mask down to leftover byte count
266 sub r2,r4,r9 // r2 <- length remaining after cache-line aligning
268 srwi. r8,r2,7 // r8 <- number of cache lines to 0
275 rlwinm r4,r2,0,0x7F // r4 <- length remaining after dcbz128'ing
H A Dhibernate_restore.s62 lwz r2,4(r4)
72 stw r2,4(r6)
123 ld r2,8(r3)
133 std r2,8(r4)
142 ld r2,72(r3)
151 std r2,72(r4)
H A Dvmachmon_asm.s371 rlwinm. r2,r28,0,0,30 ; Is there a context there? (Note: we will ignore bit 31 so that we
376 mulli r2,r4,vmmCEntrySize ; Get displacement from index
378 add r2,r2,r28 ; Point to the entry
382 swvmmDAdsp: la r2,vmmc(r2) ; Get the offset to the context array
384 lwz r4,vmmFlags(r2) ; Get the flags for the selected entry
386 lwz r5,vmmContextKern(r2) ; Get the context area address
412 stw r31,vmmPmap(r2) ; Save the last dispatched address space
421 swvmtryx: lwarx r4,r8,r2 ; Pic
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H A Dmachine_routines_asm.s44 * r2 -- new MSR
49 * Uses r0 and r2. ml_set_translation_off also uses r3 and cr5.
62 andc r2,r11,r0 // turn off EE, IR, and DR
66 mr r3,r2 // copy new MSR to r2
96 andc r2,r11,r0 // turn off DR and maybe EE
99 mtmsr r2 // turn off translation
105 rldimi r2,r0,63,MSR_SF_BIT // set SF bit (bit 0)
106 mtmsrd r2 // set 64-bit mode, turn off data relocation
166 andc r2,r
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H A Dlowmem_vectors.s992 stw r2,LTR_r2+4(r20) ; Save register
1116 std r2,LTR_r2(r20) ; Save register
1242 notsleep: stw r2,saver2+4(r13) ; Save this one
1244 rlwinm r2,r1,0,nap+1,doze-1 ; Clear any possible nap and doze bits
1245 mtspr hid0,r2 ; Clear the nap/doze bits
1250 mfsprg r2,0 ; Get the per_proc area
1265 lwz r1,spcFlags(r2) ; Load spcFlags
1269 lwz r4,FAMintercept(r2) ; Load exceptions mask to intercept
1277 lwz r1,pfAvailable(r2) ; Get the CPU features flags
1313 stw r8,ruptStamp(r2) ; Sav
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H A Dhw_vm.s668 ori r2,r2,0xFFFF ; Get mask to clean out hash table base (works for both 32- and 64-bit)
673 andc r29,r29,r2 ; Clean up hash table base
721 rlwinm r2,r21,29,29,31 ; Get slot number (8 byte entries)
726 srw r0,r0,r2 ; Get the allocation hash mask
919 addi r2,r4,-mapRemChunk ; See if mapRemChunk or more
921 srawi r2,r2,31 ; We have -1 if less than mapRemChunk or 0 if equal or more
924 cmpwi cr7,r2,0 ; Remember if we have finished
927 and r4,r4,r2 ; I
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H A Dcswtch.s147 lwz r2,umwRelo+4(r5) ; Get user memory window relocation bottom
156 stw r2,ppUMWmp+mpNestReloc+4(r12) ; Save bottom part of physical address
158 lwz r2,traceMask(0) ; Get the enabled traces
161 mr. r2,r2 ; Any tracing going on?
166 li r2,0x4400 ; Trace ID
170 cswNoTrc: lwz r2,curctx(r5) ; Grab our current context pointer
178 cmplw r10,r2 ; Do we have the live float context?
179 lwz r10,FPUlevel(r2) ; Get the live level
181 cmplw cr5,r9,r2 ; D
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H A Dbcopy.s202 srdi r2,r3,31 ; Get a 1 if source is in I/O memory
207 cmpldi cr0,r2,1 ; Is source in I/O memory?
238 mfspr r2,hid4 ; Get HID4
240 or r2,r2,r0 ; Set bit to make real accesses cache-inhibited
242 mtspr hid4,r2 ; Make real accesses cache-inhibited
256 mfspr r2,hid4 ; Get HID4
257 andc r2,r2,r0 ; Clear bit to make real accesses cache-inhibited
259 mtspr hid4,r2 ; Mak
[all...]
/macosx-10.5.8/xnu-1228.15.4/bsd/crypto/aes/i386/
H A Daes_x86_v2.s259 #define nr_xor(r1, r2, r3, r4) \
260 movzbl %r2, %r4; \
264 #define nr_mov(r1, r2, r3, r4) \
265 movzbl %r2, %r4; \
274 #define lr_xor_zo(r1, r2, r3, r4) \
275 movzbl %r2, %r4; \
279 #define lr_xor(r1, r2, r3, r4) \
280 movzbl %r2, %r4; \
285 #define lr_mov_zo(r1, r2, r3, r4) \
286 movzbl %r2,
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/macosx-10.5.8/xnu-1228.15.4/osfmk/mach/ppc/
H A D_types.h53 unsigned int r2; member in struct:ppc_thread_state
100 unsigned long long r2; member in struct:ppc_thread_state64
H A D_structs.h98 unsigned int r2; variable
197 unsigned long long r2; variable
/macosx-10.5.8/xnu-1228.15.4/bsd/sys/
H A Ddtrace.h183 #define DIF_OP_OR 1 /* or r1, r2, rd */
184 #define DIF_OP_XOR 2 /* xor r1, r2, rd */
185 #define DIF_OP_AND 3 /* and r1, r2, rd */
186 #define DIF_OP_SLL 4 /* sll r1, r2, rd */
187 #define DIF_OP_SRL 5 /* srl r1, r2, rd */
188 #define DIF_OP_SUB 6 /* sub r1, r2, rd */
189 #define DIF_OP_ADD 7 /* add r1, r2, rd */
190 #define DIF_OP_MUL 8 /* mul r1, r2, rd */
191 #define DIF_OP_SDIV 9 /* sdiv r1, r2, rd */
192 #define DIF_OP_UDIV 10 /* udiv r1, r2, r
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