Lines Matching refs:r2
116 neg r2,r12 // is destination cache-line-aligned?
121 andi. r2,r2,0x7F // #bytes to align
132 mr r5,r2 // number of bytes to copy
133 add rs,rs,r2 // then bump our parameters past initial copy
134 add rd,rd,r2
135 sub rc,rc,r2
149 srwi r2,rc,8 // get number of 256-byte chunks to xfer
156 mtctr r2 // set up loop count
158 cmpd cr7,r2,r2 // initialize cr7_eq to "on", so we dcbz128
187 addi r2,rs,128 // point to 2nd 128 bytes of source
195 lvxl v9,0,r2
197 lvxl v10,c16,r2
198 lvxl v11,c32,r2
200 lvxl v12,c48,r2
201 lvxl v13,c64,r2
203 lvxl v14,c80,r2
204 lvxl v15,c96,r2
206 lvxl v16,c112,r2
209 addi r2,rd,128 // point to 2nd 128 bytes of dest
212 dcbz128 0,r2
232 stvxl v18,0,r2
234 stvxl v19,c16,r2
236 stvxl v20,c32,r2
238 stvxl v21,c48,r2
239 stvxl v22,c64,r2
240 stvxl v23,c80,r2
241 stvxl v17,c96,r2
242 stvxl v18,c112,r2
263 addi r2,rs,128 // point to 2nd 128 bytes of source
272 lvxl v9,0,r2
273 lvxl v10,c16,r2
274 lvxl v11,c32,r2
275 lvxl v12,c48,r2
276 lvxl v13,c64,r2
277 lvxl v14,c80,r2
278 lvxl v15,c96,r2
279 lvxl v16,c112,r2
280 addi r2,rd,128 // point to 2nd 128 bytes of dest
283 dcbz128 0,r2
295 stvxl v9,0,r2
296 stvxl v10,c16,r2
297 stvxl v11,c32,r2
298 stvxl v12,c48,r2
299 stvxl v13,c64,r2
300 stvxl v14,c80,r2
301 stvxl v15,c96,r2
302 stvxl v16,c112,r2