Lines Matching refs:r2
44 * r2 -- new MSR
49 * Uses r0 and r2. ml_set_translation_off also uses r3 and cr5.
62 andc r2,r11,r0 // turn off EE, IR, and DR
66 mr r3,r2 // copy new MSR to r2
96 andc r2,r11,r0 // turn off DR and maybe EE
99 mtmsr r2 // turn off translation
105 rldimi r2,r0,63,MSR_SF_BIT // set SF bit (bit 0)
106 mtmsrd r2 // set 64-bit mode, turn off data relocation
166 andc r2,r0,r8 ; Clear VEC, FP, and EE
177 mtmsr r2 ; Translation and all off
184 mr r3,r2 ; Get new MSR
228 ori r11,r2,lo16(MASK(MSR_DR)) ; Turn on data translation
241 mtmsr r2 ; Turn translation back off
307 li r2,1 ; Get a 1
308 sldi r2,r2,63 ; Get the 64-bit bit
310 or r10,r10,r2 ; Set 64-bit
319 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
321 mtspr hid4,r2 ; Make real accesses cache-inhibited
631 li r2,1 ; Prepare for 64 bit
636 rldimi r9,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
641 sldi r0,r2,32+8 ; Get the right bit to turn off caching
646 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
648 mtspr hid4,r2 ; Make real accesses cache-inhibited
934 mipNSF1: li r2,lo16(MASK(MSR_DR)|MASK(MSR_IR)) ; Get the translation mask
937 andc r5,r5,r2 ; Clear IR and DR from current MSR
940 oris r2,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
978 rlwinm r6,r2,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Clear out the EE bit
993 mtmsr r2 ; Nap or doze, MSR with POW, EE set, translation off
1092 li r2,1 ; Prepare for 64 bit
1099 rldimi r5,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
1244 citlbhang: lwarx r2,0,r5 ; Get the TLBIE lock
1245 mr. r2,r2 ; Is it locked?
1270 cinoSMP: stw r2,tlbieLock(0) ; Unlock TLBIE lock
1313 li r2,1 ; Get a mask of 0x01
1329 cislckit: not r5,r2 ; Lock all but 1 way
1356 rlwinm. r2,r2,1,24,31 ; Shift to next way
1370 cisnlck: rlwinm r2,r0,0,1,30 ; Double cache size
1371 add r0,r0,r2 ; Get 3 times cache size
1376 ciswfldl1a: lwz r2,0(r3) ; Flush anything else
1413 xor r2,r8,r3 ; Get changing bits?
1415 and. r0,r0,r2 ; Did any change?
1444 oris r2,r8,hi16(l2dom) ; Set L2 to data only mode
1450 mtspr l2cr,r2 ; Disable L2
1492 oris r2,r8,hi16(l2im) ; Get the invalidate flag set
1494 mtspr l2cr,r2 ; Start the invalidate
1497 ciinvdl2a: mfspr r2,l2cr ; Get the L2CR
1501 rlwinm. r2,r2,0,l2i,l2i ; Is the invalidate still going?
1506 rlwinm. r2,r2,0,l2ip,l2ip ; Is the invalidate still going?
1525 xor r2,r8,r3 ; Get changing bits?
1527 and. r0,r0,r2 ; Did any change?
1574 srw r2, r8, r10 ; ?
1575 rlwimi r2, r8, 0, 24, 31 ; ?
1578 ori r2, r2, 0x0080 ; ?
1580 or r8, r2, r8 ; ?
1589 li r2,128 ; ?
1590 ciinvdl3c: addi r2,r2,-1 ; ?
1591 cmplwi r2,0 ; ?
1652 eqv r2,r2,r2 ; Get all foxes
1661 rldimi r11,r2,38,25 ; Disable D$ prefetch (25:25)
1739 rldimi r3,r2,54,9 ; Set force icbi match mode
2289 mfspr r2,hdec ; Save hdec
2297 sub r3,r2,r9 ; How many ticks?
2320 addic r2,r4,-kMin ; Subtract minimum from target
2325 subc r7,r2,r9 ; Subtract bottom and get carry
2330 addic r2,r6,-1 ; Set carry if diff < 2**32
2334 subfe r2,r2,r2 ; 0 if diff > 2**32, -1 otherwise
2336 or r2,r2,r0 ; If the duration is negative, it is not too big
2338 and r7,r7,r2 ; Clear duration if high part too big