Searched refs:dma_cfg (Results 1 - 25 of 40) sorted by relevance

12

/linux-master/include/linux/
H A Dsxgbe_platform.h45 struct sxgbe_dma_cfg *dma_cfg; member in struct:sxgbe_plat_data
/linux-master/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac1000_dma.c74 struct stmmac_dma_cfg *dma_cfg, int atds)
77 int txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
78 int rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
86 if (dma_cfg->pblx8)
94 if (dma_cfg->fixed_burst)
98 if (dma_cfg->mixed_burst)
104 if (dma_cfg->aal)
115 struct stmmac_dma_cfg *dma_cfg,
73 dwmac1000_dma_init(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, int atds) argument
113 dwmac1000_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_rx_phy, u32 chan) argument
122 dwmac1000_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_tx_phy, u32 chan) argument
[all...]
H A Ddwmac100_dma.c22 struct stmmac_dma_cfg *dma_cfg, int atds)
25 writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
33 struct stmmac_dma_cfg *dma_cfg,
41 struct stmmac_dma_cfg *dma_cfg,
21 dwmac100_dma_init(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, int atds) argument
32 dwmac100_dma_init_rx(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_rx_phy, u32 chan) argument
40 dwmac100_dma_init_tx(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_tx_phy, u32 chan) argument
H A Ddwmac4_dma.c74 struct stmmac_dma_cfg *dma_cfg,
79 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
85 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
95 struct stmmac_dma_cfg *dma_cfg,
100 u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl;
110 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) && likely(dma_cfg->eame))
120 struct stmmac_dma_cfg *dma_cfg, u32 chan)
127 if (dma_cfg
72 dwmac4_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_rx_phy, u32 chan) argument
93 dwmac4_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t dma_tx_phy, u32 chan) argument
118 dwmac4_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) argument
136 dwmac410_dma_init_channel(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) argument
155 dwmac4_dma_init(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, int atds) argument
[all...]
H A Dstmmac_pci.c61 plat->dma_cfg->pbl = 32;
62 plat->dma_cfg->pblx8 = true;
117 plat->dma_cfg->pbl = 32;
118 plat->dma_cfg->pblx8 = true;
172 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
174 if (!plat->dma_cfg)
H A Ddwmac-loongson.c41 plat->dma_cfg->pbl = 32;
42 plat->dma_cfg->pblx8 = true;
78 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
79 if (!plat->dma_cfg) {
H A Ddwxgmac2_dma.c23 struct stmmac_dma_cfg *dma_cfg, int atds)
27 if (dma_cfg->aal)
30 if (dma_cfg->eame)
38 struct stmmac_dma_cfg *dma_cfg, u32 chan)
42 if (dma_cfg->pblx8)
51 struct stmmac_dma_cfg *dma_cfg,
54 u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl;
68 struct stmmac_dma_cfg *dma_cfg,
71 u32 txpbl = dma_cfg
22 dwxgmac2_dma_init(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, int atds) argument
36 dwxgmac2_dma_init_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, u32 chan) argument
49 dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) argument
66 dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, u32 chan) argument
[all...]
H A Dstmmac_platform.c437 struct stmmac_dma_cfg *dma_cfg; local
580 dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
582 if (!dma_cfg) {
586 plat->dma_cfg = dma_cfg;
588 of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
589 if (!dma_cfg->pbl)
590 dma_cfg->pbl = DEFAULT_DMA_PBL;
591 of_property_read_u32(np, "snps,txpbl", &dma_cfg
[all...]
H A Ddwmac-intel.c510 plat->dma_cfg->pbl = 32;
511 plat->dma_cfg->pblx8 = true;
512 plat->dma_cfg->fixed_burst = 0;
513 plat->dma_cfg->mixed_burst = 0;
514 plat->dma_cfg->aal = 0;
515 plat->dma_cfg->dche = true;
928 plat->dma_cfg->pbl = 16;
929 plat->dma_cfg->pblx8 = true;
930 plat->dma_cfg->fixed_burst = 1;
1048 plat->dma_cfg
[all...]
/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_platform.c31 struct sxgbe_dma_cfg *dma_cfg; local
51 dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), GFP_KERNEL);
52 if (!dma_cfg)
55 plat->dma_cfg = dma_cfg;
56 of_property_read_u32(np, "samsung,pbl", &dma_cfg->pbl);
57 if (of_property_read_u32(np, "samsung,burst-map", &dma_cfg->burst_map) == 0)
58 dma_cfg->fixed_burst = true;
/linux-master/drivers/staging/media/atomisp/pci/css_2401_system/
H A Dibuf_ctrl_global.h59 } dma_cfg; member in struct:ibuf_ctrl_cfg_s
/linux-master/drivers/usb/musb/
H A Dtusb6010_omap.c197 struct dma_slave_config dma_cfg; local
270 memset(&dma_cfg, 0, sizeof(dma_cfg));
274 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
275 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
278 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
279 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
290 dma_cfg.src_addr = fifo_addr;
291 dma_cfg.dst_addr = fifo_addr;
292 dma_cfg
[all...]
/linux-master/drivers/mmc/host/
H A Dcavium-thunderx.c174 u64 dma_cfg; local
181 dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
182 dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
183 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
H A Dowl-mmc.c112 struct dma_slave_config dma_cfg; member in struct:owl_mmc_host
311 owl_host->dma_cfg.direction = DMA_MEM_TO_DEV;
314 owl_host->dma_cfg.direction = DMA_DEV_TO_MEM;
320 dmaengine_slave_config(owl_host->dma, &owl_host->dma_cfg);
323 owl_host->dma_cfg.direction,
633 owl_host->dma_cfg.src_addr = res->start + OWL_REG_SD_DAT;
634 owl_host->dma_cfg.dst_addr = res->start + OWL_REG_SD_DAT;
635 owl_host->dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
636 owl_host->dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
637 owl_host->dma_cfg
[all...]
H A Dcavium-octeon.c302 u64 dma_cfg; local
309 dma_cfg = readq(host->dma_base + MIO_EMM_DMA_CFG(host));
310 dma_cfg &= ~MIO_EMM_DMA_CFG_EN;
311 writeq(dma_cfg, host->dma_base + MIO_EMM_DMA_CFG(host));
/linux-master/drivers/ata/
H A Dpata_octeon_cf.c595 union cvmx_mio_boot_dma_cfgx dma_cfg; local
604 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
605 if (dma_cfg.s.size != 0xfffff) {
612 dma_cfg.u64 = 0;
613 dma_cfg.s.size = -1;
614 cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64);
653 union cvmx_mio_boot_dma_cfgx dma_cfg; local
659 dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG);
666 if (dma_int.s.done && !dma_cfg.s.en) {
976 union cvmx_mio_boot_dma_cfgx dma_cfg; local
[all...]
/linux-master/drivers/staging/media/atomisp/pci/
H A Disp2401_input_system_global.h62 isys2401_dma_cfg_t dma_cfg; member in struct:input_system_channel_cfg_s
/linux-master/drivers/dma/
H A Dste_dma40.c472 * @dma_cfg: The client configuration of this dma channel.
474 * @configured: whether the dma_cfg configuration is valid
499 struct stedma40_chan_cfg dma_cfg; member in struct:d40_chan
881 chan->dma_cfg.dir == DMA_DEV_TO_MEM))
1264 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1267 if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1268 (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1272 if (d40c->dma_cfg.dir != DMA_DEV_TO_MEM)
1366 return phy_map[d40c->dma_cfg.mode_opt];
1368 return log_map[d40c->dma_cfg
[all...]
/linux-master/drivers/spi/
H A Dspi-stm32-qspi.c700 struct dma_slave_config dma_cfg; local
704 memset(&dma_cfg, 0, sizeof(dma_cfg));
706 dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
707 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
708 dma_cfg.src_addr = qspi->phys_base + QSPI_DR;
709 dma_cfg.dst_addr = qspi->phys_base + QSPI_DR;
710 dma_cfg.src_maxburst = 4;
711 dma_cfg.dst_maxburst = 4;
720 if (dmaengine_slave_config(qspi->dma_chrx, &dma_cfg)) {
[all...]
/linux-master/drivers/comedi/drivers/
H A Dni_660x.c264 unsigned int dma_cfg[NI660X_MAX_CHIPS]; member in struct:ni_660x_private
316 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
317 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL(mite_channel,
319 ni_660x_write(dev, chip, devpriv->dma_cfg[chip] |
331 devpriv->dma_cfg[chip] &= ~NI660X_DMA_CFG_SEL_MASK(mite_channel);
332 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(mite_channel);
333 ni_660x_write(dev, chip, devpriv->dma_cfg[chip], NI660X_DMA_CFG);
984 devpriv->dma_cfg[chip] = 0;
986 devpriv->dma_cfg[chip] |= NI660X_DMA_CFG_SEL_NONE(chan);
987 ni_660x_write(dev, chip, devpriv->dma_cfg[chi
[all...]
/linux-master/drivers/staging/media/atomisp/pci/runtime/isys/src/
H A Dvirtual_isys.c467 &channel_cfg->dma_cfg);
708 cfg->dma_cfg.channel = channel->dma_channel;
709 cfg->dma_cfg.cmd = _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND;
711 cfg->dma_cfg.shift_returned_items = 0;
712 cfg->dma_cfg.elems_per_word_in_ibuf = 0;
713 cfg->dma_cfg.elems_per_word_in_dest = 0;
/linux-master/drivers/mtd/nand/raw/
H A Dstm32_fmc2_nand.c351 struct dma_slave_config dma_cfg; local
362 memset(&dma_cfg, 0, sizeof(dma_cfg));
363 dma_cfg.dst_addr = nfc->data_phys_addr[nfc->cs_sel];
364 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
365 dma_cfg.dst_maxburst = nfc->tx_dma_max_burst /
366 dma_cfg.dst_addr_width;
368 ret = dmaengine_slave_config(nfc->dma_tx_ch, &dma_cfg);
376 memset(&dma_cfg, 0, sizeof(dma_cfg));
[all...]
/linux-master/arch/mips/loongson32/common/
H A Dplatform.c136 .dma_cfg = &ls1x_eth_dma_cfg,
173 .dma_cfg = &ls1x_eth_dma_cfg,
/linux-master/drivers/leds/
H A Dleds-sun50i-a100.c390 struct dma_slave_config dma_cfg = {}; local
477 dma_cfg.dst_addr = mem->start + LEDC_DATA_REG;
478 dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
479 dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2;
481 ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
/linux-master/drivers/gpu/drm/kmb/
H A Dkmb_plane.c354 unsigned int dma_cfg; local
522 dma_cfg = LCD_DMA_LAYER_ENABLE | LCD_DMA_LAYER_VSTRIDE_EN |
526 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
537 drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg,

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