Searched refs:dclk (Results 1 - 25 of 93) sorted by relevance

1234

/linux-master/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon_dclk.c28 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
30 regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
36 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
38 return regmap_update_bits(dclk->regmap, SUN4I_TCON0_DCLK_REG,
45 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
48 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
56 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
59 regmap_read(dclk->regmap, SUN4I_TCON0_DCLK_REG, &val);
73 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
74 struct sun4i_tcon *tcon = dclk
118 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
127 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
140 struct sun4i_dclk *dclk = hw_to_dclk(hw); local
169 struct sun4i_dclk *dclk; local
[all...]
/linux-master/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c49 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); local
51 val = readl_relaxed(dclk->reg) >> dclk->shift;
52 val &= div_mask(dclk->width);
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table,
55 CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
61 struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw); local
63 return divider_round_rate(hw, rate, prate, dclk->table,
64 dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
73 struct hi6220_clk_divider *dclk local
[all...]
/linux-master/drivers/clk/nuvoton/
H A Dclk-ma35d1-divider.c33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); local
35 val = readl_relaxed(dclk->reg) >> dclk->shift;
36 val &= clk_div_mask(dclk->width);
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table,
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
44 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw); local
46 return divider_round_rate(hw, rate, prate, dclk->table,
47 dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
55 struct ma35d1_adc_clk_div *dclk local
[all...]
/linux-master/drivers/siox/
H A Dsiox-bus-gpio.c20 struct gpio_desc *dclk; member in struct:siox_gpio_ddata
38 gpiod_set_value_cansleep(ddata->dclk, 0);
60 gpiod_set_value_cansleep(ddata->dclk, 1);
62 gpiod_set_value_cansleep(ddata->dclk, 0);
112 ddata->dclk = devm_gpiod_get(dev, "dclk", GPIOD_OUT_LOW);
113 if (IS_ERR(ddata->dclk))
114 return dev_err_probe(dev, PTR_ERR(ddata->dclk),
115 "Failed to get dclk GPIO\n");
/linux-master/drivers/gpu/drm/renesas/rz-du/
H A Drzg2l_du_crtc.h61 struct clk *dclk; member in struct:rzg2l_du_crtc::__anon513
H A Drzg2l_du_crtc.c71 clk_prepare_enable(rcrtc->rzg2l_clocks.dclk);
72 clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock);
209 clk_disable_unprepare(rcrtc->rzg2l_clocks.dclk);
401 rcrtc->rzg2l_clocks.dclk = devm_clk_get(rcdu->dev, "vclk");
402 if (IS_ERR(rcrtc->rzg2l_clocks.dclk)) {
404 return PTR_ERR(rcrtc->rzg2l_clocks.dclk);
/linux-master/drivers/clk/
H A Dclk-lmk04832.c246 * @dclk: list of internal device clock references.
267 struct lmk_dclk *dclk; member in struct:lmk04832
715 * and dclk
1013 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); local
1014 struct lmk04832 *lmk = dclk->lmk;
1018 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1028 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); local
1029 struct lmk04832 *lmk = dclk->lmk;
1032 LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1038 struct lmk_dclk *dclk local
1049 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); local
1075 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); local
1097 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); local
[all...]
/linux-master/drivers/video/fbdev/riva/
H A Dnv_driver.c276 unsigned long dclk = 0; local
286 dclk = 800000;
288 dclk = 1000000;
294 dclk = 1000000;
303 dclk = 800000;
306 dclk = 1000000;
311 return dclk;
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_bw.c22 u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; member in struct:intel_qgv_point
53 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
57 sp->dclk *= 2;
59 if (sp->dclk == 0)
80 u16 dclk; local
89 dclk = val & 0xffff;
90 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),
181 u16 dclk; local
187 dclk
334 u16 dclk = 0; local
[all...]
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr_ppt.h59 uint32_t dclk; /* UVD D-clock */ member in struct:phm_ppt_v1_mm_clock_voltage_dependency_record
H A Dsmu8_hwmgr.h115 uint32_t dclk; member in struct:smu8_uvd_clocks
H A Dsmu7_hwmgr.h69 uint32_t dclk; member in struct:smu7_uvd_clocks
/linux-master/sound/soc/meson/
H A Daxg-pdm.c94 struct clk *dclk; member in struct:axg_pdm
186 /* Max sample counter value per half period of dclk */
188 clk_get_rate(priv->dclk) * 2);
253 ret = clk_set_rate(priv->dclk, rate * os);
255 dev_err(dai->dev, "failed to set dclk\n");
276 ret = clk_prepare_enable(priv->dclk);
278 dev_err(dai->dev, "enabling dclk failed\n");
294 clk_disable_unprepare(priv->dclk);
618 priv->dclk = devm_clk_get(dev, "dclk");
[all...]
/linux-master/drivers/gpu/drm/radeon/
H A Drs780_dpm.c571 (new_ps->dclk == old_ps->dclk))
577 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
588 (new_ps->dclk == old_ps->dclk))
594 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
728 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
731 rps->dclk = 0;
735 if ((rps->vclk == 0) || (rps->dclk == 0)) {
737 rps->dclk
[all...]
H A Dtrinity_dpm.h69 u32 dclk; member in struct:trinity_uvd_clock_table_entry
H A Dtrinity_dpm.c850 if ((rps->vclk == 0) && (rps->dclk == 0))
863 (rps1->dclk == rps2->dclk) &&
895 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
906 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
1411 (rps->dclk == pi->sys_info.uvd_clock_table_entries[i].dclk))
1645 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1648 rps->dclk = 0;
1890 pi->sys_info.uvd_clock_table_entries[i].dclk
[all...]
H A Drv770_dpm.c1441 (new_ps->dclk == old_ps->dclk))
1447 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
1458 (new_ps->dclk == old_ps->dclk))
1464 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
2156 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2159 rps->dclk = 0;
2163 if ((rps->vclk == 0) || (rps->dclk == 0)) {
2165 rps->dclk
[all...]
/linux-master/drivers/video/fbdev/core/
H A Dfbmon.c1017 u32 dclk; member in struct:__fb_timings
1087 * @dclk: pixelclock in Hz
1099 * where: h_period = SQRT(100 - C + (0.4 * xres * M)/dclk) + C - 100
1105 static u32 fb_get_hblank_by_dclk(u32 dclk, u32 xres) argument
1109 dclk /= 1000;
1112 h_period += (M_VAL * xres * 2 * 1000)/(5 * dclk);
1156 timings->dclk = timings->htotal * timings->hfreq;
1167 timings->dclk = timings->htotal * timings->hfreq;
1172 timings->hblank = fb_get_hblank_by_dclk(timings->dclk,
1175 timings->hfreq = timings->dclk/timing
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h39 uint32_t dclk; member in struct:__anon156
120 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
/linux-master/sound/soc/intel/skylake/
H A Dskl-ssp-clk.c278 static void unregister_src_clk(struct skl_clk_data *dclk) argument
280 while (dclk->avail_clk_cnt--)
281 clkdev_drop(dclk->clk[dclk->avail_clk_cnt]->lookup);
/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h185 unsigned long dclk; member in struct:pp_clock_engine_request
/linux-master/include/linux/mfd/
H A Dsi476x-platform.h121 enum si476x_dclk_config dclk; member in struct:si476x_pinmux
/linux-master/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_vangogh.h121 uint32_t dclk; member in struct:__anon511
149 uint8_t VcnClkLevelsEnabled; //applies to both vclk/dclk
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h66 struct dm_pp_clock_range dclk; member in struct:dm_pp_gpu_clock_range
/linux-master/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.c176 /* vop dclk */
177 struct clk *dclk; member in struct:vop
181 /* vop dclk reset */
634 ret = clk_enable(vop->dclk);
702 clk_disable(vop->dclk);
775 clk_disable(vop->dclk);
1243 rate = clk_round_rate(vop->dclk, adjusted_mode->clock * 1000);
1245 rate = clk_round_rate(vop->dclk,
1477 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
2013 vop->dclk
[all...]

Completed in 398 milliseconds

1234