1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * include/media/si476x-platform.h -- Platform data specific definitions
4 *
5 * Copyright (C) 2013 Andrey Smirnov
6 *
7 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
8 */
9
10#ifndef __SI476X_PLATFORM_H__
11#define __SI476X_PLATFORM_H__
12
13/* It is possible to select one of the four addresses using pins A0
14 * and A1 on SI476x */
15#define SI476X_I2C_ADDR_1	0x60
16#define SI476X_I2C_ADDR_2	0x61
17#define SI476X_I2C_ADDR_3	0x62
18#define SI476X_I2C_ADDR_4	0x63
19
20enum si476x_iqclk_config {
21	SI476X_IQCLK_NOOP = 0,
22	SI476X_IQCLK_TRISTATE = 1,
23	SI476X_IQCLK_IQ = 21,
24};
25enum si476x_iqfs_config {
26	SI476X_IQFS_NOOP = 0,
27	SI476X_IQFS_TRISTATE = 1,
28	SI476X_IQFS_IQ = 21,
29};
30enum si476x_iout_config {
31	SI476X_IOUT_NOOP = 0,
32	SI476X_IOUT_TRISTATE = 1,
33	SI476X_IOUT_OUTPUT = 22,
34};
35enum si476x_qout_config {
36	SI476X_QOUT_NOOP = 0,
37	SI476X_QOUT_TRISTATE = 1,
38	SI476X_QOUT_OUTPUT = 22,
39};
40
41enum si476x_dclk_config {
42	SI476X_DCLK_NOOP      = 0,
43	SI476X_DCLK_TRISTATE  = 1,
44	SI476X_DCLK_DAUDIO    = 10,
45};
46
47enum si476x_dfs_config {
48	SI476X_DFS_NOOP      = 0,
49	SI476X_DFS_TRISTATE  = 1,
50	SI476X_DFS_DAUDIO    = 10,
51};
52
53enum si476x_dout_config {
54	SI476X_DOUT_NOOP       = 0,
55	SI476X_DOUT_TRISTATE   = 1,
56	SI476X_DOUT_I2S_OUTPUT = 12,
57	SI476X_DOUT_I2S_INPUT  = 13,
58};
59
60enum si476x_xout_config {
61	SI476X_XOUT_NOOP        = 0,
62	SI476X_XOUT_TRISTATE    = 1,
63	SI476X_XOUT_I2S_INPUT   = 13,
64	SI476X_XOUT_MODE_SELECT = 23,
65};
66
67enum si476x_icin_config {
68	SI476X_ICIN_NOOP	= 0,
69	SI476X_ICIN_TRISTATE	= 1,
70	SI476X_ICIN_GPO1_HIGH	= 2,
71	SI476X_ICIN_GPO1_LOW	= 3,
72	SI476X_ICIN_IC_LINK	= 30,
73};
74
75enum si476x_icip_config {
76	SI476X_ICIP_NOOP	= 0,
77	SI476X_ICIP_TRISTATE	= 1,
78	SI476X_ICIP_GPO2_HIGH	= 2,
79	SI476X_ICIP_GPO2_LOW	= 3,
80	SI476X_ICIP_IC_LINK	= 30,
81};
82
83enum si476x_icon_config {
84	SI476X_ICON_NOOP	= 0,
85	SI476X_ICON_TRISTATE	= 1,
86	SI476X_ICON_I2S		= 10,
87	SI476X_ICON_IC_LINK	= 30,
88};
89
90enum si476x_icop_config {
91	SI476X_ICOP_NOOP	= 0,
92	SI476X_ICOP_TRISTATE	= 1,
93	SI476X_ICOP_I2S		= 10,
94	SI476X_ICOP_IC_LINK	= 30,
95};
96
97
98enum si476x_lrout_config {
99	SI476X_LROUT_NOOP	= 0,
100	SI476X_LROUT_TRISTATE	= 1,
101	SI476X_LROUT_AUDIO	= 2,
102	SI476X_LROUT_MPX	= 3,
103};
104
105
106enum si476x_intb_config {
107	SI476X_INTB_NOOP     = 0,
108	SI476X_INTB_TRISTATE = 1,
109	SI476X_INTB_DAUDIO   = 10,
110	SI476X_INTB_IRQ      = 40,
111};
112
113enum si476x_a1_config {
114	SI476X_A1_NOOP     = 0,
115	SI476X_A1_TRISTATE = 1,
116	SI476X_A1_IRQ      = 40,
117};
118
119
120struct si476x_pinmux {
121	enum si476x_dclk_config  dclk;
122	enum si476x_dfs_config   dfs;
123	enum si476x_dout_config  dout;
124	enum si476x_xout_config  xout;
125
126	enum si476x_iqclk_config iqclk;
127	enum si476x_iqfs_config  iqfs;
128	enum si476x_iout_config  iout;
129	enum si476x_qout_config  qout;
130
131	enum si476x_icin_config  icin;
132	enum si476x_icip_config  icip;
133	enum si476x_icon_config  icon;
134	enum si476x_icop_config  icop;
135
136	enum si476x_lrout_config lrout;
137
138	enum si476x_intb_config  intb;
139	enum si476x_a1_config    a1;
140};
141
142enum si476x_ibias6x {
143	SI476X_IBIAS6X_OTHER			= 0,
144	SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK	= 1,
145};
146
147enum si476x_xstart {
148	SI476X_XSTART_MULTIPLE_TUNER	= 0x11,
149	SI476X_XSTART_NORMAL		= 0x77,
150};
151
152enum si476x_freq {
153	SI476X_FREQ_4_MHZ		= 0,
154	SI476X_FREQ_37P209375_MHZ	= 1,
155	SI476X_FREQ_36P4_MHZ		= 2,
156	SI476X_FREQ_37P8_MHZ		=  3,
157};
158
159enum si476x_xmode {
160	SI476X_XMODE_CRYSTAL_RCVR1	= 1,
161	SI476X_XMODE_EXT_CLOCK		= 2,
162	SI476X_XMODE_CRYSTAL_RCVR2_3	= 3,
163};
164
165enum si476x_xbiashc {
166	SI476X_XBIASHC_SINGLE_RECEIVER = 0,
167	SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
168};
169
170enum si476x_xbias {
171	SI476X_XBIAS_RCVR2_3	= 0,
172	SI476X_XBIAS_4MHZ_RCVR1 = 3,
173	SI476X_XBIAS_RCVR1	= 7,
174};
175
176enum si476x_func {
177	SI476X_FUNC_BOOTLOADER	= 0,
178	SI476X_FUNC_FM_RECEIVER = 1,
179	SI476X_FUNC_AM_RECEIVER = 2,
180	SI476X_FUNC_WB_RECEIVER = 3,
181};
182
183
184/**
185 * @xcload: Selects the amount of additional on-chip capacitance to
186 *          be connected between XTAL1 and gnd and between XTAL2 and
187 *          GND. One half of the capacitance value shown here is the
188 *          additional load capacitance presented to the xtal. The
189 *          minimum step size is 0.277 pF. Recommended value is 0x28
190 *          but it will be layout dependent. Range is 0���0x3F i.e.
191 *          (0���16.33 pF)
192 * @ctsien: enable CTSINT(interrupt request when CTS condition
193 *          arises) when set
194 * @intsel: when set A1 pin becomes the interrupt pin; otherwise,
195 *          INTB is the interrupt pin
196 * @func:   selects the boot function of the device. I.e.
197 *          SI476X_BOOTLOADER  - Boot loader
198 *          SI476X_FM_RECEIVER - FM receiver
199 *          SI476X_AM_RECEIVER - AM receiver
200 *          SI476X_WB_RECEIVER - Weatherband receiver
201 * @freq:   oscillator's crystal frequency:
202 *          SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
203 *          SI476X_XTAL_36P4_MHZ      - 36.4 Mhz
204 *          SI476X_XTAL_37P8_MHZ      - 37.8 Mhz
205 */
206struct si476x_power_up_args {
207	enum si476x_ibias6x ibias6x;
208	enum si476x_xstart  xstart;
209	u8   xcload;
210	bool fastboot;
211	enum si476x_xbiashc xbiashc;
212	enum si476x_xbias   xbias;
213	enum si476x_func    func;
214	enum si476x_freq    freq;
215	enum si476x_xmode   xmode;
216};
217
218
219/**
220 * enum si476x_phase_diversity_mode - possbile phase diversity modes
221 * for SI4764/5/6/7 chips.
222 *
223 * @SI476X_PHDIV_DISABLED:		Phase diversity feature is
224 *					disabled.
225 * @SI476X_PHDIV_PRIMARY_COMBINING:	Tuner works as a primary tuner
226 *					in combination with a
227 *					secondary one.
228 * @SI476X_PHDIV_PRIMARY_ANTENNA:	Tuner works as a primary tuner
229 *					using only its own antenna.
230 * @SI476X_PHDIV_SECONDARY_ANTENNA:	Tuner works as a primary tuner
231 *					usning seconary tuner's antenna.
232 * @SI476X_PHDIV_SECONDARY_COMBINING:	Tuner works as a secondary
233 *					tuner in combination with the
234 *					primary one.
235 */
236enum si476x_phase_diversity_mode {
237	SI476X_PHDIV_DISABLED			= 0,
238	SI476X_PHDIV_PRIMARY_COMBINING		= 1,
239	SI476X_PHDIV_PRIMARY_ANTENNA		= 2,
240	SI476X_PHDIV_SECONDARY_ANTENNA		= 3,
241	SI476X_PHDIV_SECONDARY_COMBINING	= 5,
242};
243
244
245/*
246 * Platform dependent definition
247 */
248struct si476x_platform_data {
249	int gpio_reset; /* < 0 if not used */
250
251	struct si476x_power_up_args power_up_parameters;
252	enum si476x_phase_diversity_mode diversity_mode;
253
254	struct si476x_pinmux pinmux;
255};
256
257
258#endif /* __SI476X_PLATFORM_H__ */
259