1// SPDX-License-Identifier: GPL-2.0 2/* 3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner 4 * Pin compatible with the LMK0482x family 5 * 6 * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf 7 * 8 * Copyright (c) 2020, Xiphos Systems Corp. 9 * 10 */ 11 12#include <linux/bitfield.h> 13#include <linux/clk.h> 14#include <linux/clk-provider.h> 15#include <linux/device.h> 16#include <linux/gcd.h> 17#include <linux/gpio/consumer.h> 18#include <linux/module.h> 19#include <linux/regmap.h> 20#include <linux/spi/spi.h> 21 22/* 0x000 - 0x00d System Functions */ 23#define LMK04832_REG_RST3W 0x000 24#define LMK04832_BIT_RESET BIT(7) 25#define LMK04832_BIT_SPI_3WIRE_DIS BIT(4) 26#define LMK04832_REG_POWERDOWN 0x002 27#define LMK04832_REG_ID_DEV_TYPE 0x003 28#define LMK04832_REG_ID_PROD_MSB 0x004 29#define LMK04832_REG_ID_PROD_LSB 0x005 30#define LMK04832_REG_ID_MASKREV 0x006 31#define LMK04832_REG_ID_VNDR_MSB 0x00c 32#define LMK04832_REG_ID_VNDR_LSB 0x00d 33 34/* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */ 35#define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8) 36#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0) 37#define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8) 38#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0) 39#define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8) 40#define LMK04832_BIT_CLKOUTX_Y_PD BIT(7) 41#define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4) 42#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2) 43#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0) 44#define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8) 45#define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5) 46#define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8) 47#define LMK04832_BIT_DCLKX_Y_PD BIT(4) 48#define LMK04832_BIT_DCLKX_Y_DCC BIT(2) 49#define LMK04832_BIT_DCLKX_Y_HS BIT(0) 50#define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8) 51#define LMK04832_BIT_SCLK_PD BIT(4) 52#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2) 53#define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8) 54#define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8) 55#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0) 56#define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8) 57#define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f) 58#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00 59#define LMK04832_VAL_CLKOUT_FMT_LVDS 0x01 60#define LMK04832_VAL_CLKOUT_FMT_HSDS6 0x02 61#define LMK04832_VAL_CLKOUT_FMT_HSDS8 0x03 62#define LMK04832_VAL_CLKOUT_FMT_LVPECL1600 0x04 63#define LMK04832_VAL_CLKOUT_FMT_LVPECL2000 0x05 64#define LMK04832_VAL_CLKOUT_FMT_LCPECL 0x06 65#define LMK04832_VAL_CLKOUT_FMT_CML16 0x07 66#define LMK04832_VAL_CLKOUT_FMT_CML24 0x08 67#define LMK04832_VAL_CLKOUT_FMT_CML32 0x09 68#define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV 0x0a 69#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF 0x0b 70#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV 0x0c 71#define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR 0x0d 72#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV 0x0e 73#define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR 0x0f 74 75/* 0x138 - 0x145 SYSREF, SYNC, and Device Config */ 76#define LMK04832_REG_VCO_OSCOUT 0x138 77#define LMK04832_BIT_VCO_MUX GENMASK(6, 5) 78#define LMK04832_VAL_VCO_MUX_VCO0 0x00 79#define LMK04832_VAL_VCO_MUX_VCO1 0x01 80#define LMK04832_VAL_VCO_MUX_EXT 0x02 81#define LMK04832_REG_SYSREF_OUT 0x139 82#define LMK04832_BIT_SYSREF_REQ_EN BIT(6) 83#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0) 84#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00 85#define LMK04832_VAL_SYSREF_MUX_RECLK 0x01 86#define LMK04832_VAL_SYSREF_MUX_PULSER 0x02 87#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03 88#define LMK04832_REG_SYSREF_DIV_MSB 0x13a 89#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0) 90#define LMK04832_REG_SYSREF_DIV_LSB 0x13b 91#define LMK04832_REG_SYSREF_DDLY_MSB 0x13c 92#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0) 93#define LMK04832_REG_SYSREF_DDLY_LSB 0x13d 94#define LMK04832_REG_SYSREF_PULSE_CNT 0x13e 95#define LMK04832_REG_FB_CTRL 0x13f 96#define LMK04832_BIT_PLL2_RCLK_MUX BIT(7) 97#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00 98#define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN 0x01 99#define LMK04832_BIT_PLL2_NCLK_MUX BIT(5) 100#define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P 0x00 101#define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX 0x01 102#define LMK04832_BIT_FB_MUX_EN BIT(0) 103#define LMK04832_REG_MAIN_PD 0x140 104#define LMK04832_BIT_PLL1_PD BIT(7) 105#define LMK04832_BIT_VCO_LDO_PD BIT(6) 106#define LMK04832_BIT_VCO_PD BIT(5) 107#define LMK04832_BIT_OSCIN_PD BIT(4) 108#define LMK04832_BIT_SYSREF_GBL_PD BIT(3) 109#define LMK04832_BIT_SYSREF_PD BIT(2) 110#define LMK04832_BIT_SYSREF_DDLY_PD BIT(1) 111#define LMK04832_BIT_SYSREF_PLSR_PD BIT(0) 112#define LMK04832_REG_SYNC 0x143 113#define LMK04832_BIT_SYNC_CLR BIT(7) 114#define LMK04832_BIT_SYNC_1SHOT_EN BIT(6) 115#define LMK04832_BIT_SYNC_POL BIT(5) 116#define LMK04832_BIT_SYNC_EN BIT(4) 117#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0) 118#define LMK04832_VAL_SYNC_MODE_OFF 0x00 119#define LMK04832_VAL_SYNC_MODE_ON 0x01 120#define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02 121#define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03 122#define LMK04832_REG_SYNC_DIS 0x144 123 124/* 0x146 - 0x14a CLKin Control */ 125#define LMK04832_REG_CLKIN_SEL0 0x148 126#define LMK04832_REG_CLKIN_SEL1 0x149 127#define LMK04832_REG_CLKIN_RST 0x14a 128#define LMK04832_BIT_SDIO_RDBK_TYPE BIT(6) 129#define LMK04832_BIT_CLKIN_SEL_MUX GENMASK(5, 3) 130#define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK 0x06 131#define LMK04832_BIT_CLKIN_SEL_TYPE GENMASK(2, 0) 132#define LMK04832_VAL_CLKIN_SEL_TYPE_OUT 0x03 133 134/* 0x14b - 0x152 Holdover */ 135 136/* 0x153 - 0x15f PLL1 Configuration */ 137#define LMK04832_REG_PLL1_LD 0x15f 138#define LMK04832_BIT_PLL1_LD_MUX GENMASK(7, 3) 139#define LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK 0x07 140#define LMK04832_BIT_PLL1_LD_TYPE GENMASK(2, 0) 141#define LMK04832_VAL_PLL1_LD_TYPE_OUT_PP 0x03 142 143/* 0x160 - 0x16e PLL2 Configuration */ 144#define LMK04832_REG_PLL2_R_MSB 0x160 145#define LMK04832_BIT_PLL2_R_MSB GENMASK(3, 0) 146#define LMK04832_REG_PLL2_R_LSB 0x161 147#define LMK04832_REG_PLL2_MISC 0x162 148#define LMK04832_BIT_PLL2_MISC_P GENMASK(7, 5) 149#define LMK04832_BIT_PLL2_MISC_REF_2X_EN BIT(0) 150#define LMK04832_REG_PLL2_N_CAL_0 0x163 151#define LMK04832_BIT_PLL2_N_CAL_0 GENMASK(1, 0) 152#define LMK04832_REG_PLL2_N_CAL_1 0x164 153#define LMK04832_REG_PLL2_N_CAL_2 0x165 154#define LMK04832_REG_PLL2_N_0 0x166 155#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0) 156#define LMK04832_REG_PLL2_N_1 0x167 157#define LMK04832_REG_PLL2_N_2 0x168 158#define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a 159#define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b 160#define LMK04832_REG_PLL2_LD 0x16e 161#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3) 162#define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD 0x02 163#define LMK04832_BIT_PLL2_LD_TYPE GENMASK(2, 0) 164#define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP 0x03 165 166/* 0x16F - 0x555 Misc Registers */ 167#define LMK04832_REG_PLL2_PD 0x173 168#define LMK04832_BIT_PLL2_PRE_PD BIT(6) 169#define LMK04832_BIT_PLL2_PD BIT(5) 170#define LMK04832_REG_PLL1R_RST 0x177 171#define LMK04832_REG_CLR_PLL_LOST 0x182 172#define LMK04832_REG_RB_PLL_LD 0x183 173#define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184 174#define LMK04832_REG_RB_DAC_VAL_LSB 0x185 175#define LMK04832_REG_RB_HOLDOVER 0x188 176#define LMK04832_REG_SPI_LOCK 0x555 177 178enum lmk04832_device_types { 179 LMK04832, 180}; 181 182/** 183 * struct lmk04832_device_info - Holds static device information that is 184 * specific to the chip revision 185 * 186 * @pid: Product Identifier 187 * @maskrev: IC version identifier 188 * @num_channels: Number of available output channels (clkout count) 189 * @vco0_range: {min, max} of the VCO0 operating range (in MHz) 190 * @vco1_range: {min, max} of the VCO1 operating range (in MHz) 191 */ 192struct lmk04832_device_info { 193 u16 pid; 194 u8 maskrev; 195 size_t num_channels; 196 unsigned int vco0_range[2]; 197 unsigned int vco1_range[2]; 198}; 199 200static const struct lmk04832_device_info lmk04832_device_info[] = { 201 [LMK04832] = { 202 .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */ 203 .maskrev = 0x70, 204 .num_channels = 14, 205 .vco0_range = { 2440, 2580 }, 206 .vco1_range = { 2945, 3255 }, 207 }, 208}; 209 210enum lmk04832_rdbk_type { 211 RDBK_CLKIN_SEL0, 212 RDBK_CLKIN_SEL1, 213 RDBK_RESET, 214 RDBK_PLL1_LD, 215}; 216 217struct lmk_dclk { 218 struct lmk04832 *lmk; 219 struct clk_hw hw; 220 u8 id; 221}; 222 223struct lmk_clkout { 224 struct lmk04832 *lmk; 225 struct clk_hw hw; 226 bool sysref; 227 u32 format; 228 u8 id; 229}; 230 231/** 232 * struct lmk04832 - The LMK04832 device structure 233 * 234 * @dev: reference to a struct device, linked to the spi_device 235 * @regmap: struct regmap instance use to access the chip 236 * @sync_mode: operational mode for SYNC signal 237 * @sysref_mux: select SYSREF source 238 * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous 239 * mode. 240 * @sysref_ddly: SYSREF digital delay value 241 * @oscin: PLL2 input clock 242 * @vco: reference to the internal VCO clock 243 * @sclk: reference to the internal sysref clock (SCLK) 244 * @vco_rate: user provided VCO rate 245 * @reset_gpio: reference to the reset GPIO 246 * @dclk: list of internal device clock references. 247 * Each pair of clkout clocks share a single device clock (DCLKX_Y) 248 * @clkout: list of output clock references 249 * @clk_data: holds clkout related data like clk_hw* and number of clocks 250 */ 251struct lmk04832 { 252 struct device *dev; 253 struct regmap *regmap; 254 255 unsigned int sync_mode; 256 unsigned int sysref_mux; 257 unsigned int sysref_pulse_cnt; 258 unsigned int sysref_ddly; 259 260 struct clk *oscin; 261 struct clk_hw vco; 262 struct clk_hw sclk; 263 unsigned int vco_rate; 264 265 struct gpio_desc *reset_gpio; 266 267 struct lmk_dclk *dclk; 268 struct lmk_clkout *clkout; 269 struct clk_hw_onecell_data *clk_data; 270}; 271 272static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg) 273{ 274 switch (reg) { 275 case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV: 276 case LMK04832_REG_ID_VNDR_MSB: 277 case LMK04832_REG_ID_VNDR_LSB: 278 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: 279 case LMK04832_REG_PLL2_LD: 280 case LMK04832_REG_PLL2_PD: 281 case LMK04832_REG_PLL1R_RST: 282 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: 283 case LMK04832_REG_RB_HOLDOVER: 284 case LMK04832_REG_SPI_LOCK: 285 return true; 286 default: 287 return false; 288 }; 289} 290 291static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg) 292{ 293 switch (reg) { 294 case LMK04832_REG_RST3W: 295 case LMK04832_REG_POWERDOWN: 296 return true; 297 case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV: 298 case LMK04832_REG_ID_VNDR_MSB: 299 case LMK04832_REG_ID_VNDR_LSB: 300 return false; 301 case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB: 302 case LMK04832_REG_PLL2_LD: 303 case LMK04832_REG_PLL2_PD: 304 case LMK04832_REG_PLL1R_RST: 305 case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB: 306 case LMK04832_REG_RB_HOLDOVER: 307 case LMK04832_REG_SPI_LOCK: 308 return true; 309 default: 310 return false; 311 }; 312} 313 314static const struct regmap_config regmap_config = { 315 .name = "lmk04832", 316 .reg_bits = 16, 317 .val_bits = 8, 318 .use_single_read = 1, 319 .use_single_write = 1, 320 .read_flag_mask = 0x80, 321 .write_flag_mask = 0x00, 322 .readable_reg = lmk04832_regmap_rd_regs, 323 .writeable_reg = lmk04832_regmap_wr_regs, 324 .cache_type = REGCACHE_NONE, 325 .max_register = LMK04832_REG_SPI_LOCK, 326}; 327 328static int lmk04832_vco_is_enabled(struct clk_hw *hw) 329{ 330 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 331 unsigned int tmp; 332 int ret; 333 334 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); 335 if (ret) 336 return ret; 337 338 return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) | 339 FIELD_GET(LMK04832_BIT_VCO_PD, tmp) | 340 FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp)); 341} 342 343static int lmk04832_vco_prepare(struct clk_hw *hw) 344{ 345 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 346 int ret; 347 348 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, 349 LMK04832_BIT_PLL2_PRE_PD | 350 LMK04832_BIT_PLL2_PD, 351 0x00); 352 if (ret) 353 return ret; 354 355 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 356 LMK04832_BIT_VCO_LDO_PD | 357 LMK04832_BIT_VCO_PD | 358 LMK04832_BIT_OSCIN_PD, 0x00); 359} 360 361static void lmk04832_vco_unprepare(struct clk_hw *hw) 362{ 363 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 364 365 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, 366 LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD, 367 0xff); 368 369 /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */ 370 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 371 LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff); 372} 373 374static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw, 375 unsigned long prate) 376{ 377 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 378 const unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7}; 379 unsigned int pll2_n, p, pll2_r; 380 unsigned int pll2_misc; 381 unsigned long vco_rate; 382 u8 tmp[3]; 383 int ret; 384 385 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); 386 if (ret) 387 return ret; 388 389 p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc); 390 391 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); 392 if (ret) 393 return ret; 394 395 pll2_n = FIELD_PREP(0x030000, tmp[0]) | 396 FIELD_PREP(0x00ff00, tmp[1]) | 397 FIELD_PREP(0x0000ff, tmp[2]); 398 399 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); 400 if (ret) 401 return ret; 402 403 pll2_r = FIELD_PREP(0x0f00, tmp[0]) | 404 FIELD_PREP(0x00ff, tmp[1]); 405 406 vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN, 407 pll2_misc)) * pll2_n * pll2_p[p] / pll2_r; 408 409 return vco_rate; 410} 411 412/** 413 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges 414 * 415 * @lmk: Reference to the lmk device 416 * @rate: Desired output rate for the VCO 417 * 418 * The LMK04832 has 2 internal VCO, each with independent operating ranges. 419 * Use the device_info structure to determine which VCO to use based on rate. 420 * 421 * Returns: VCO_MUX value or negative errno. 422 */ 423static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate) 424{ 425 struct spi_device *spi = to_spi_device(lmk->dev); 426 const struct lmk04832_device_info *info; 427 unsigned long mhz = rate / 1000000; 428 429 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; 430 431 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) 432 return LMK04832_VAL_VCO_MUX_VCO0; 433 434 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) 435 return LMK04832_VAL_VCO_MUX_VCO1; 436 437 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); 438 return -ERANGE; 439} 440 441/** 442 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency 443 * 444 * @prate: parent rate to the PLL2, usually OSCin 445 * @rate: Desired output rate for the VCO 446 * @n: reference to PLL2_N 447 * @p: reference to PLL2_P 448 * @r: reference to PLL2_R 449 * 450 * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is 451 * recommended in the datasheet because a higher phase detector frequencies 452 * makes the design of wider loop bandwidth filters possible. 453 * 454 * the VCO rate can be calculated using the following expression: 455 * 456 * VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R 457 * 458 * Returns: vco rate or negative errno. 459 */ 460static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate, 461 unsigned int *n, unsigned int *p, 462 unsigned int *r) 463{ 464 unsigned int pll2_n, pll2_p, pll2_r; 465 unsigned long num, div; 466 467 /* Set PLL2_P to a fixed value to simplify optimizations */ 468 pll2_p = 2; 469 470 div = gcd(rate, prate); 471 472 num = DIV_ROUND_CLOSEST(rate, div); 473 pll2_r = DIV_ROUND_CLOSEST(prate, div); 474 475 if (num > 4) { 476 pll2_n = num >> 2; 477 } else { 478 pll2_r = pll2_r << 2; 479 pll2_n = num; 480 } 481 482 if (pll2_n < 1 || pll2_n > 0x03ffff) 483 return -EINVAL; 484 if (pll2_r < 1 || pll2_r > 0xfff) 485 return -EINVAL; 486 487 *n = pll2_n; 488 *p = pll2_p; 489 *r = pll2_r; 490 491 return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r); 492} 493 494static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate, 495 unsigned long *prate) 496{ 497 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 498 unsigned int n, p, r; 499 long vco_rate; 500 int ret; 501 502 ret = lmk04832_check_vco_ranges(lmk, rate); 503 if (ret < 0) 504 return ret; 505 506 vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r); 507 if (vco_rate < 0) { 508 dev_err(lmk->dev, "PLL2 parameters out of range\n"); 509 return vco_rate; 510 } 511 512 if (rate != vco_rate) 513 return -EINVAL; 514 515 return vco_rate; 516} 517 518static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate, 519 unsigned long prate) 520{ 521 struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco); 522 unsigned int n, p, r; 523 long vco_rate; 524 int vco_mux; 525 int ret; 526 527 vco_mux = lmk04832_check_vco_ranges(lmk, rate); 528 if (vco_mux < 0) 529 return vco_mux; 530 531 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, 532 LMK04832_BIT_VCO_MUX, 533 FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux)); 534 if (ret) 535 return ret; 536 537 vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r); 538 if (vco_rate < 0) { 539 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); 540 return vco_rate; 541 } 542 543 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, 544 LMK04832_BIT_PLL2_R_MSB, 545 FIELD_GET(0x000700, r)); 546 if (ret) 547 return ret; 548 549 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, 550 FIELD_GET(0x0000ff, r)); 551 if (ret) 552 return ret; 553 554 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, 555 LMK04832_BIT_PLL2_MISC_P, 556 FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p)); 557 if (ret) 558 return ret; 559 560 /* 561 * PLL2_N registers must be programmed after other PLL2 dividers are 562 * programmed to ensure proper VCO frequency calibration 563 */ 564 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, 565 FIELD_GET(0x030000, n)); 566 if (ret) 567 return ret; 568 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, 569 FIELD_GET(0x00ff00, n)); 570 if (ret) 571 return ret; 572 573 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, 574 FIELD_GET(0x0000ff, n)); 575} 576 577static const struct clk_ops lmk04832_vco_ops = { 578 .is_enabled = lmk04832_vco_is_enabled, 579 .prepare = lmk04832_vco_prepare, 580 .unprepare = lmk04832_vco_unprepare, 581 .recalc_rate = lmk04832_vco_recalc_rate, 582 .round_rate = lmk04832_vco_round_rate, 583 .set_rate = lmk04832_vco_set_rate, 584}; 585 586/* 587 * lmk04832_register_vco - Initialize the internal VCO and clock distribution 588 * path in PLL2 single loop mode. 589 */ 590static int lmk04832_register_vco(struct lmk04832 *lmk) 591{ 592 const char *parent_names[1]; 593 struct clk_init_data init; 594 int ret; 595 596 init.name = "lmk-vco"; 597 parent_names[0] = __clk_get_name(lmk->oscin); 598 init.parent_names = parent_names; 599 600 init.ops = &lmk04832_vco_ops; 601 init.num_parents = 1; 602 603 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, 604 LMK04832_BIT_VCO_MUX, 605 FIELD_PREP(LMK04832_BIT_VCO_MUX, 606 LMK04832_VAL_VCO_MUX_VCO1)); 607 if (ret) 608 return ret; 609 610 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, 611 LMK04832_BIT_PLL2_RCLK_MUX | 612 LMK04832_BIT_PLL2_NCLK_MUX, 613 FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX, 614 LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)| 615 FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX, 616 LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P)); 617 if (ret) 618 return ret; 619 620 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, 621 LMK04832_BIT_PLL2_MISC_REF_2X_EN, 622 LMK04832_BIT_PLL2_MISC_REF_2X_EN); 623 if (ret) 624 return ret; 625 626 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, 627 FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX, 628 LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) | 629 FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE, 630 LMK04832_VAL_PLL2_LD_TYPE_OUT_PP)); 631 if (ret) 632 return ret; 633 634 lmk->vco.init = &init; 635 return devm_clk_hw_register(lmk->dev, &lmk->vco); 636} 637 638static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id) 639{ 640 const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; 641 unsigned int sclkx_y_ddly = 10; 642 unsigned int dclkx_y_ddly; 643 unsigned int dclkx_y_div; 644 unsigned int sysref_ddly; 645 unsigned int dclkx_y_hs; 646 unsigned int lsb, msb; 647 int ret; 648 649 ret = regmap_update_bits(lmk->regmap, 650 LMK04832_REG_CLKOUT_CTRL2(id), 651 LMK04832_BIT_DCLKX_Y_DDLY_PD, 652 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0)); 653 if (ret) 654 return ret; 655 656 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); 657 if (ret) 658 return ret; 659 660 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); 661 if (ret) 662 return ret; 663 664 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb; 665 666 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); 667 if (ret) 668 return ret; 669 670 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); 671 if (ret) 672 return ret; 673 674 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; 675 676 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); 677 if (ret) 678 return ret; 679 680 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb); 681 682 dclkx_y_ddly = sysref_ddly + 1 - 683 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - 684 dclkx_y_hs + sclkx_y_ddly; 685 686 if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) { 687 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", 688 dclkx_y_ddly); 689 return -EINVAL; 690 } 691 692 ret = regmap_write(lmk->regmap, 693 LMK04832_REG_SCLKX_Y_DDLY(id), 694 FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly)); 695 if (ret) 696 return ret; 697 698 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), 699 FIELD_GET(0x00ff, dclkx_y_ddly)); 700 if (ret) 701 return ret; 702 703 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " 704 "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n", 705 id, sysref_ddly, dclkx_y_ddly, 706 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7], 707 dclkx_y_hs, sclkx_y_ddly); 708 709 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), 710 LMK04832_BIT_DCLKX_Y_DDLY_MSB, 711 FIELD_GET(0x0300, dclkx_y_ddly)); 712} 713 714/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk 715 * and dclk 716 * 717 * @lmk: Reference to the lmk device 718 * 719 * The synchronization sequence: 720 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31 721 * (8.3.3.1 How to enable SYSREF) 722 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972 723 * 724 * Returns 0 or negative errno. 725 */ 726static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk) 727{ 728 int ret; 729 int i; 730 731 /* 1. (optional) mute all sysref_outputs during synchronization */ 732 /* 2. Enable and write device clock digital delay to applicable clocks */ 733 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 734 LMK04832_BIT_SYSREF_DDLY_PD, 735 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0)); 736 if (ret) 737 return ret; 738 739 for (i = 0; i < lmk->clk_data->num; i += 2) { 740 ret = lmk04832_clkout_set_ddly(lmk, i); 741 if (ret) 742 return ret; 743 } 744 745 /* 746 * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC, 747 * and clear SYSREF_REQ_EN (see 6.) 748 */ 749 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 750 LMK04832_BIT_SYSREF_REQ_EN | 751 LMK04832_BIT_SYSREF_MUX, 752 FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) | 753 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 754 LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC)); 755 if (ret) 756 return ret; 757 758 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 759 LMK04832_BIT_SYNC_MODE, 760 FIELD_PREP(LMK04832_BIT_SYNC_MODE, 761 LMK04832_VAL_SYNC_MODE_ON)); 762 if (ret) 763 return ret; 764 765 /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */ 766 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); 767 if (ret) 768 return ret; 769 770 /* 771 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock 772 * distribution path cycles (VCO cycles), then back to 0. In 773 * PLL2-only use case, this will be complete in less than one SPI 774 * transaction. If SYSREF local digital delay is not used, this step 775 * can be skipped. 776 */ 777 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 778 LMK04832_BIT_SYNC_CLR, 779 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01)); 780 if (ret) 781 return ret; 782 783 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 784 LMK04832_BIT_SYNC_CLR, 785 FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00)); 786 if (ret) 787 return ret; 788 789 /* 790 * 6. Toggle SYNC_POL state between inverted and not inverted. 791 * If you use an external signal on the SYNC pin instead of toggling 792 * SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX 793 * does not shift into continuous SYSREF mode. 794 */ 795 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 796 LMK04832_BIT_SYNC_POL, 797 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01)); 798 if (ret) 799 return ret; 800 801 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 802 LMK04832_BIT_SYNC_POL, 803 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00)); 804 if (ret) 805 return ret; 806 807 /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */ 808 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); 809 if (ret) 810 return ret; 811 812 /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */ 813 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 814 LMK04832_BIT_SYSREF_MUX, 815 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 816 lmk->sysref_mux)); 817 if (ret) 818 return ret; 819 820 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, 821 LMK04832_BIT_SYNC_MODE, 822 FIELD_PREP(LMK04832_BIT_SYNC_MODE, 823 lmk->sync_mode)); 824 if (ret) 825 return ret; 826 827 /* 828 * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs 829 * during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state, 830 * or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional 831 * option. 832 */ 833 834 /* 835 * 10. (optional) To reduce power consumption, after the synchronization 836 * event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the 837 * digital delay counters (which are only used immediately after the 838 * SYNC pulse to delay the output by some number of VCO counts). 839 */ 840 841 return ret; 842} 843 844static int lmk04832_sclk_is_enabled(struct clk_hw *hw) 845{ 846 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 847 unsigned int tmp; 848 int ret; 849 850 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); 851 if (ret) 852 return ret; 853 854 return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp); 855} 856 857static int lmk04832_sclk_prepare(struct clk_hw *hw) 858{ 859 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 860 861 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 862 LMK04832_BIT_SYSREF_PD, 0x00); 863} 864 865static void lmk04832_sclk_unprepare(struct clk_hw *hw) 866{ 867 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 868 869 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 870 LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD); 871} 872 873static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw, 874 unsigned long prate) 875{ 876 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 877 unsigned int sysref_div; 878 u8 tmp[2]; 879 int ret; 880 881 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); 882 if (ret) 883 return ret; 884 885 sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 | 886 tmp[1]; 887 888 return DIV_ROUND_CLOSEST(prate, sysref_div); 889} 890 891static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate, 892 unsigned long *prate) 893{ 894 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 895 unsigned long sclk_rate; 896 unsigned int sysref_div; 897 898 sysref_div = DIV_ROUND_CLOSEST(*prate, rate); 899 sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div); 900 901 if (sysref_div < 0x07 || sysref_div > 0x1fff) { 902 dev_err(lmk->dev, "SYSREF divider out of range\n"); 903 return -EINVAL; 904 } 905 906 if (rate != sclk_rate) 907 return -EINVAL; 908 909 return sclk_rate; 910} 911 912static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate, 913 unsigned long prate) 914{ 915 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk); 916 unsigned int sysref_div; 917 int ret; 918 919 sysref_div = DIV_ROUND_CLOSEST(prate, rate); 920 921 if (sysref_div < 0x07 || sysref_div > 0x1fff) { 922 dev_err(lmk->dev, "SYSREF divider out of range\n"); 923 return -EINVAL; 924 } 925 926 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, 927 FIELD_GET(0x1f00, sysref_div)); 928 if (ret) 929 return ret; 930 931 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, 932 FIELD_GET(0x00ff, sysref_div)); 933 if (ret) 934 return ret; 935 936 ret = lmk04832_sclk_sync_sequence(lmk); 937 if (ret) 938 dev_err(lmk->dev, "SYNC sequence failed\n"); 939 940 return ret; 941} 942 943static const struct clk_ops lmk04832_sclk_ops = { 944 .is_enabled = lmk04832_sclk_is_enabled, 945 .prepare = lmk04832_sclk_prepare, 946 .unprepare = lmk04832_sclk_unprepare, 947 .recalc_rate = lmk04832_sclk_recalc_rate, 948 .round_rate = lmk04832_sclk_round_rate, 949 .set_rate = lmk04832_sclk_set_rate, 950}; 951 952static int lmk04832_register_sclk(struct lmk04832 *lmk) 953{ 954 const char *parent_names[1]; 955 struct clk_init_data init; 956 int ret; 957 958 init.name = "lmk-sclk"; 959 parent_names[0] = clk_hw_get_name(&lmk->vco); 960 init.parent_names = parent_names; 961 962 init.ops = &lmk04832_sclk_ops; 963 init.flags = CLK_SET_RATE_PARENT; 964 init.num_parents = 1; 965 966 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, 967 LMK04832_BIT_SYSREF_MUX, 968 FIELD_PREP(LMK04832_BIT_SYSREF_MUX, 969 lmk->sysref_mux)); 970 if (ret) 971 return ret; 972 973 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, 974 FIELD_GET(0x00ff, lmk->sysref_ddly)); 975 if (ret) 976 return ret; 977 978 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, 979 FIELD_GET(0x1f00, lmk->sysref_ddly)); 980 if (ret) 981 return ret; 982 983 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, 984 ilog2(lmk->sysref_pulse_cnt)); 985 if (ret) 986 return ret; 987 988 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, 989 LMK04832_BIT_SYSREF_DDLY_PD | 990 LMK04832_BIT_SYSREF_PLSR_PD, 991 FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) | 992 FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0)); 993 if (ret) 994 return ret; 995 996 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, 997 FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) | 998 FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) | 999 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); 1000 if (ret) 1001 return ret; 1002 1003 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); 1004 if (ret) 1005 return ret; 1006 1007 lmk->sclk.init = &init; 1008 return devm_clk_hw_register(lmk->dev, &lmk->sclk); 1009} 1010 1011static int lmk04832_dclk_is_enabled(struct clk_hw *hw) 1012{ 1013 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1014 struct lmk04832 *lmk = dclk->lmk; 1015 unsigned int tmp; 1016 int ret; 1017 1018 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1019 &tmp); 1020 if (ret) 1021 return ret; 1022 1023 return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp); 1024} 1025 1026static int lmk04832_dclk_prepare(struct clk_hw *hw) 1027{ 1028 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1029 struct lmk04832 *lmk = dclk->lmk; 1030 1031 return regmap_update_bits(lmk->regmap, 1032 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1033 LMK04832_BIT_DCLKX_Y_PD, 0x00); 1034} 1035 1036static void lmk04832_dclk_unprepare(struct clk_hw *hw) 1037{ 1038 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1039 struct lmk04832 *lmk = dclk->lmk; 1040 1041 regmap_update_bits(lmk->regmap, 1042 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1043 LMK04832_BIT_DCLKX_Y_PD, 0xff); 1044} 1045 1046static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw, 1047 unsigned long prate) 1048{ 1049 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1050 struct lmk04832 *lmk = dclk->lmk; 1051 unsigned int dclk_div; 1052 unsigned int lsb, msb; 1053 unsigned long rate; 1054 int ret; 1055 1056 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), 1057 &lsb); 1058 if (ret) 1059 return ret; 1060 1061 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1062 &msb); 1063 if (ret) 1064 return ret; 1065 1066 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; 1067 rate = DIV_ROUND_CLOSEST(prate, dclk_div); 1068 1069 return rate; 1070} 1071 1072static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate, 1073 unsigned long *prate) 1074{ 1075 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1076 struct lmk04832 *lmk = dclk->lmk; 1077 unsigned long dclk_rate; 1078 unsigned int dclk_div; 1079 1080 dclk_div = DIV_ROUND_CLOSEST(*prate, rate); 1081 dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div); 1082 1083 if (dclk_div < 1 || dclk_div > 0x3ff) { 1084 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); 1085 return -EINVAL; 1086 } 1087 1088 if (rate != dclk_rate) 1089 return -EINVAL; 1090 1091 return dclk_rate; 1092} 1093 1094static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate, 1095 unsigned long prate) 1096{ 1097 struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw); 1098 struct lmk04832 *lmk = dclk->lmk; 1099 unsigned int dclk_div; 1100 int ret; 1101 1102 dclk_div = DIV_ROUND_CLOSEST(prate, rate); 1103 1104 if (dclk_div > 0x3ff) { 1105 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); 1106 return -EINVAL; 1107 } 1108 1109 /* Enable Duty Cycle Correction */ 1110 if (dclk_div == 1) { 1111 ret = regmap_update_bits(lmk->regmap, 1112 LMK04832_REG_CLKOUT_CTRL3(dclk->id), 1113 LMK04832_BIT_DCLKX_Y_DCC, 1114 FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1)); 1115 if (ret) 1116 return ret; 1117 } 1118 1119 /* 1120 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC 1121 * procedure requires to first program Divide-by-4 and then back to 1122 * Divide-by-2 or Divide-by-3 before doing SYNC. 1123 */ 1124 if (dclk_div == 2 || dclk_div == 3) { 1125 ret = regmap_update_bits(lmk->regmap, 1126 LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1127 LMK04832_BIT_DCLK_DIV_MSB, 0x00); 1128 if (ret) 1129 return ret; 1130 1131 ret = regmap_write(lmk->regmap, 1132 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); 1133 if (ret) 1134 return ret; 1135 } 1136 1137 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), 1138 FIELD_GET(0x0ff, dclk_div)); 1139 if (ret) 1140 return ret; 1141 1142 ret = regmap_update_bits(lmk->regmap, 1143 LMK04832_REG_CLKOUT_CTRL2(dclk->id), 1144 LMK04832_BIT_DCLK_DIV_MSB, 1145 FIELD_GET(0x300, dclk_div)); 1146 if (ret) 1147 return ret; 1148 1149 ret = lmk04832_sclk_sync_sequence(lmk); 1150 if (ret) 1151 dev_err(lmk->dev, "SYNC sequence failed\n"); 1152 1153 return ret; 1154} 1155 1156static const struct clk_ops lmk04832_dclk_ops = { 1157 .is_enabled = lmk04832_dclk_is_enabled, 1158 .prepare = lmk04832_dclk_prepare, 1159 .unprepare = lmk04832_dclk_unprepare, 1160 .recalc_rate = lmk04832_dclk_recalc_rate, 1161 .round_rate = lmk04832_dclk_round_rate, 1162 .set_rate = lmk04832_dclk_set_rate, 1163}; 1164 1165static int lmk04832_clkout_is_enabled(struct clk_hw *hw) 1166{ 1167 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1168 struct lmk04832 *lmk = clkout->lmk; 1169 unsigned int clkoutx_y_pd; 1170 unsigned int sclkx_y_pd; 1171 unsigned int tmp; 1172 u32 enabled; 1173 int ret; 1174 u8 fmt; 1175 1176 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), 1177 &clkoutx_y_pd); 1178 if (ret) 1179 return ret; 1180 1181 enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd); 1182 1183 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1184 &tmp); 1185 if (ret) 1186 return ret; 1187 1188 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { 1189 ret = regmap_read(lmk->regmap, 1190 LMK04832_REG_CLKOUT_CTRL4(clkout->id), 1191 &sclkx_y_pd); 1192 if (ret) 1193 return ret; 1194 1195 enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd); 1196 } 1197 1198 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), 1199 &tmp); 1200 if (ret) 1201 return ret; 1202 1203 if (clkout->id % 2) 1204 fmt = FIELD_GET(0xf0, tmp); 1205 else 1206 fmt = FIELD_GET(0x0f, tmp); 1207 1208 return enabled && !fmt; 1209} 1210 1211static int lmk04832_clkout_prepare(struct clk_hw *hw) 1212{ 1213 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1214 struct lmk04832 *lmk = clkout->lmk; 1215 unsigned int tmp; 1216 int ret; 1217 1218 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) 1219 dev_err(lmk->dev, "prepared %s but format is powerdown\n", 1220 clk_hw_get_name(hw)); 1221 1222 ret = regmap_update_bits(lmk->regmap, 1223 LMK04832_REG_CLKOUT_CTRL2(clkout->id), 1224 LMK04832_BIT_CLKOUTX_Y_PD, 0x00); 1225 if (ret) 1226 return ret; 1227 1228 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1229 &tmp); 1230 if (ret) 1231 return ret; 1232 1233 if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) { 1234 ret = regmap_update_bits(lmk->regmap, 1235 LMK04832_REG_CLKOUT_CTRL4(clkout->id), 1236 LMK04832_BIT_SCLK_PD, 0x00); 1237 if (ret) 1238 return ret; 1239 } 1240 1241 return regmap_update_bits(lmk->regmap, 1242 LMK04832_REG_CLKOUT_FMT(clkout->id), 1243 LMK04832_BIT_CLKOUT_FMT(clkout->id), 1244 clkout->format << 4 * (clkout->id % 2)); 1245} 1246 1247static void lmk04832_clkout_unprepare(struct clk_hw *hw) 1248{ 1249 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1250 struct lmk04832 *lmk = clkout->lmk; 1251 1252 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), 1253 LMK04832_BIT_CLKOUT_FMT(clkout->id), 1254 0x00); 1255} 1256 1257static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index) 1258{ 1259 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1260 struct lmk04832 *lmk = clkout->lmk; 1261 1262 return regmap_update_bits(lmk->regmap, 1263 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1264 LMK04832_BIT_CLKOUT_SRC_MUX, 1265 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, 1266 index)); 1267} 1268 1269static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw) 1270{ 1271 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); 1272 struct lmk04832 *lmk = clkout->lmk; 1273 unsigned int tmp; 1274 int ret; 1275 1276 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), 1277 &tmp); 1278 if (ret) 1279 return ret; 1280 1281 return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp); 1282} 1283 1284static const struct clk_ops lmk04832_clkout_ops = { 1285 .is_enabled = lmk04832_clkout_is_enabled, 1286 .prepare = lmk04832_clkout_prepare, 1287 .unprepare = lmk04832_clkout_unprepare, 1288 .determine_rate = __clk_mux_determine_rate, 1289 .set_parent = lmk04832_clkout_set_parent, 1290 .get_parent = lmk04832_clkout_get_parent, 1291}; 1292 1293static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num) 1294{ 1295 char name[] = "lmk-clkoutXX"; 1296 char dclk_name[] = "lmk-dclkXX_YY"; 1297 const char *parent_names[2]; 1298 struct clk_init_data init; 1299 int dclk_num = num / 2; 1300 int ret; 1301 1302 if (num % 2 == 0) { 1303 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); 1304 init.name = dclk_name; 1305 parent_names[0] = clk_hw_get_name(&lmk->vco); 1306 init.parent_names = parent_names; 1307 init.ops = &lmk04832_dclk_ops; 1308 init.flags = CLK_SET_RATE_PARENT; 1309 init.num_parents = 1; 1310 1311 lmk->dclk[dclk_num].id = num; 1312 lmk->dclk[dclk_num].lmk = lmk; 1313 lmk->dclk[dclk_num].hw.init = &init; 1314 1315 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); 1316 if (ret) 1317 return ret; 1318 } else { 1319 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); 1320 } 1321 1322 if (of_property_read_string_index(lmk->dev->of_node, 1323 "clock-output-names", 1324 num, &init.name)) { 1325 sprintf(name, "lmk-clkout%02d", num); 1326 init.name = name; 1327 } 1328 1329 parent_names[0] = dclk_name; 1330 parent_names[1] = clk_hw_get_name(&lmk->sclk); 1331 init.parent_names = parent_names; 1332 init.ops = &lmk04832_clkout_ops; 1333 init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT; 1334 init.num_parents = ARRAY_SIZE(parent_names); 1335 1336 lmk->clkout[num].id = num; 1337 lmk->clkout[num].lmk = lmk; 1338 lmk->clkout[num].hw.init = &init; 1339 lmk->clk_data->hws[num] = &lmk->clkout[num].hw; 1340 1341 /* Set initial parent */ 1342 regmap_update_bits(lmk->regmap, 1343 LMK04832_REG_CLKOUT_SRC_MUX(num), 1344 LMK04832_BIT_CLKOUT_SRC_MUX, 1345 FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX, 1346 lmk->clkout[num].sysref)); 1347 1348 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); 1349} 1350 1351static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin) 1352{ 1353 int reg; 1354 int ret; 1355 int val = FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX, 1356 LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) | 1357 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE, 1358 LMK04832_VAL_CLKIN_SEL_TYPE_OUT); 1359 1360 dev_info(lmk->dev, "setting up 4-wire mode\n"); 1361 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, 1362 LMK04832_BIT_SPI_3WIRE_DIS); 1363 if (ret) 1364 return ret; 1365 1366 switch (rdbk_pin) { 1367 case RDBK_CLKIN_SEL0: 1368 reg = LMK04832_REG_CLKIN_SEL0; 1369 break; 1370 case RDBK_CLKIN_SEL1: 1371 reg = LMK04832_REG_CLKIN_SEL1; 1372 break; 1373 case RDBK_RESET: 1374 reg = LMK04832_REG_CLKIN_RST; 1375 break; 1376 case RDBK_PLL1_LD: 1377 reg = LMK04832_REG_PLL1_LD; 1378 val = FIELD_PREP(LMK04832_BIT_PLL1_LD_MUX, 1379 LMK04832_VAL_PLL1_LD_MUX_SPI_RDBK) | 1380 FIELD_PREP(LMK04832_BIT_PLL1_LD_TYPE, 1381 LMK04832_VAL_PLL1_LD_TYPE_OUT_PP); 1382 break; 1383 default: 1384 return -EINVAL; 1385 } 1386 1387 return regmap_write(lmk->regmap, reg, val); 1388} 1389 1390static int lmk04832_probe(struct spi_device *spi) 1391{ 1392 const struct lmk04832_device_info *info; 1393 int rdbk_pin = RDBK_CLKIN_SEL1; 1394 struct device_node *child; 1395 struct lmk04832 *lmk; 1396 u8 tmp[3]; 1397 int ret; 1398 int i; 1399 1400 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; 1401 1402 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); 1403 if (!lmk) 1404 return -ENOMEM; 1405 1406 lmk->dev = &spi->dev; 1407 1408 lmk->oscin = devm_clk_get(lmk->dev, "oscin"); 1409 if (IS_ERR(lmk->oscin)) { 1410 dev_err(lmk->dev, "failed to get oscin clock\n"); 1411 return PTR_ERR(lmk->oscin); 1412 } 1413 1414 ret = clk_prepare_enable(lmk->oscin); 1415 if (ret) 1416 return ret; 1417 1418 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 1419 GPIOD_OUT_LOW); 1420 1421 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, 1422 sizeof(struct lmk_dclk), GFP_KERNEL); 1423 if (!lmk->dclk) { 1424 ret = -ENOMEM; 1425 goto err_disable_oscin; 1426 } 1427 1428 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, 1429 sizeof(*lmk->clkout), GFP_KERNEL); 1430 if (!lmk->clkout) { 1431 ret = -ENOMEM; 1432 goto err_disable_oscin; 1433 } 1434 1435 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, 1436 info->num_channels), 1437 GFP_KERNEL); 1438 if (!lmk->clk_data) { 1439 ret = -ENOMEM; 1440 goto err_disable_oscin; 1441 } 1442 1443 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); 1444 1445 lmk->sysref_ddly = 8; 1446 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); 1447 1448 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; 1449 device_property_read_u32(lmk->dev, "ti,sysref-mux", 1450 &lmk->sysref_mux); 1451 1452 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; 1453 device_property_read_u32(lmk->dev, "ti,sync-mode", 1454 &lmk->sync_mode); 1455 1456 lmk->sysref_pulse_cnt = 4; 1457 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", 1458 &lmk->sysref_pulse_cnt); 1459 1460 for_each_child_of_node(lmk->dev->of_node, child) { 1461 int reg; 1462 1463 ret = of_property_read_u32(child, "reg", ®); 1464 if (ret) { 1465 dev_err(lmk->dev, "missing reg property in child: %s\n", 1466 child->full_name); 1467 of_node_put(child); 1468 goto err_disable_oscin; 1469 } 1470 1471 of_property_read_u32(child, "ti,clkout-fmt", 1472 &lmk->clkout[reg].format); 1473 1474 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 1475 && reg != 8 && reg != 10) 1476 dev_err(lmk->dev, "invalid format for clkout%02d\n", 1477 reg); 1478 1479 lmk->clkout[reg].sysref = 1480 of_property_read_bool(child, "ti,clkout-sysref"); 1481 } 1482 1483 lmk->regmap = devm_regmap_init_spi(spi, ®map_config); 1484 if (IS_ERR(lmk->regmap)) { 1485 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", 1486 1487 __func__, PTR_ERR(lmk->regmap)); 1488 ret = PTR_ERR(lmk->regmap); 1489 goto err_disable_oscin; 1490 } 1491 1492 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); 1493 1494 if (!(spi->mode & SPI_3WIRE)) { 1495 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", 1496 &rdbk_pin); 1497 ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin); 1498 if (ret) 1499 goto err_disable_oscin; 1500 } 1501 1502 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); 1503 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { 1504 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", 1505 tmp[0] << 8 | tmp[1], tmp[2]); 1506 ret = -EINVAL; 1507 goto err_disable_oscin; 1508 } 1509 1510 ret = lmk04832_register_vco(lmk); 1511 if (ret) { 1512 dev_err(lmk->dev, "failed to init device clock path\n"); 1513 goto err_disable_oscin; 1514 } 1515 1516 if (lmk->vco_rate) { 1517 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); 1518 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); 1519 if (ret) { 1520 dev_err(lmk->dev, "failed to set VCO rate\n"); 1521 goto err_disable_oscin; 1522 } 1523 } 1524 1525 ret = lmk04832_register_sclk(lmk); 1526 if (ret) { 1527 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); 1528 goto err_disable_oscin; 1529 } 1530 1531 for (i = 0; i < info->num_channels; i++) { 1532 ret = lmk04832_register_clkout(lmk, i); 1533 if (ret) { 1534 dev_err(lmk->dev, "failed to register clk %d\n", i); 1535 goto err_disable_oscin; 1536 } 1537 } 1538 1539 lmk->clk_data->num = info->num_channels; 1540 ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get, 1541 lmk->clk_data); 1542 if (ret) { 1543 dev_err(lmk->dev, "failed to add provider (%d)\n", ret); 1544 goto err_disable_oscin; 1545 } 1546 1547 spi_set_drvdata(spi, lmk); 1548 1549 return 0; 1550 1551err_disable_oscin: 1552 clk_disable_unprepare(lmk->oscin); 1553 1554 return ret; 1555} 1556 1557static void lmk04832_remove(struct spi_device *spi) 1558{ 1559 struct lmk04832 *lmk = spi_get_drvdata(spi); 1560 1561 clk_disable_unprepare(lmk->oscin); 1562} 1563 1564static const struct spi_device_id lmk04832_id[] = { 1565 { "lmk04832", LMK04832 }, 1566 {} 1567}; 1568MODULE_DEVICE_TABLE(spi, lmk04832_id); 1569 1570static const struct of_device_id lmk04832_of_id[] = { 1571 { .compatible = "ti,lmk04832" }, 1572 {} 1573}; 1574MODULE_DEVICE_TABLE(of, lmk04832_of_id); 1575 1576static struct spi_driver lmk04832_driver = { 1577 .driver = { 1578 .name = "lmk04832", 1579 .of_match_table = lmk04832_of_id, 1580 }, 1581 .probe = lmk04832_probe, 1582 .remove = lmk04832_remove, 1583 .id_table = lmk04832_id, 1584}; 1585module_spi_driver(lmk04832_driver); 1586 1587MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>"); 1588MODULE_DESCRIPTION("Texas Instruments LMK04832"); 1589MODULE_LICENSE("GPL v2"); 1590