/linux-master/tools/testing/selftests/timens/ |
H A D | timens.c | 37 static struct test_clock clocks[] = { variable in typeref:struct:test_clock 94 if (check_skip(clocks[clock_index].id)) 97 switch (clocks[clock_index].id) { 107 if (_gettime(clocks[clock_index].id, &parent_ts_old, raw_syscall)) 116 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) 122 clocks[clock_index].name, entry, parent_ts_old.tv_sec, 130 if (_gettime(clocks[clock_index].id, &cur_ts, raw_syscall)) 136 clocks[clock_index].name, entry, parent_ts_old.tv_sec, 139 clock_settime(clocks[clock_index].id, &cur_ts); 144 clocks[clock_inde [all...] |
/linux-master/arch/arm64/boot/dts/sprd/ |
H A D | sharkl64.dtsi | 30 clocks = <&clk26mhz>; 38 clocks = <&clk26mhz>; 46 clocks = <&clk26mhz>; 54 clocks = <&clk26mhz>;
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/linux-master/drivers/media/platform/samsung/s5p-mfc/ |
H A D | s5p_mfc_pm.c | 29 pm->clocks[i] = devm_clk_get(pm->device, pm->clk_names[i]); 30 if (IS_ERR(pm->clocks[i])) { 31 /* additional clocks are optional */ 32 if (i && PTR_ERR(pm->clocks[i]) == -ENOENT) { 33 pm->clocks[i] = NULL; 38 return PTR_ERR(pm->clocks[i]); 43 pm->clock_gate = pm->clocks[0]; 74 ret = clk_prepare_enable(dev->pm.clocks[i]); 88 clk_disable_unprepare(dev->pm.clocks[i]); 101 clk_disable_unprepare(dev->pm.clocks[ [all...] |
/linux-master/drivers/clk/bcm/ |
H A D | clk-bcm21664.c | 17 .clocks = CLOCKS("ref_crystal"), 35 .clocks = CLOCKS("bbl_32k", 59 .clocks = CLOCKS("ref_crystal", 71 .clocks = CLOCKS("ref_crystal", 83 .clocks = CLOCKS("ref_crystal", 95 .clocks = CLOCKS("ref_crystal", 106 .clocks = CLOCKS("ref_32k"), /* Verify */ 111 .clocks = CLOCKS("ref_32k"), /* Verify */ 116 .clocks = CLOCKS("ref_32k"), /* Verify */ 121 .clocks [all...] |
H A D | clk-bcm281xx.c | 19 .clocks = CLOCKS("ref_crystal"), 35 .clocks = CLOCKS("bbl_32k", 44 .clocks = CLOCKS("ref_crystal", 53 .clocks = CLOCKS("var_312m", 77 .clocks = CLOCKS("ref_crystal", 96 .clocks = CLOCKS("ref_crystal", 108 .clocks = CLOCKS("ref_crystal", 120 .clocks = CLOCKS("ref_crystal", 132 .clocks = CLOCKS("ref_crystal", 144 .clocks [all...] |
/linux-master/sound/soc/qcom/qdsp6/ |
H A D | Makefile | 2 snd-q6dsp-common-y := q6dsp-common.o q6dsp-lpass-ports.o q6dsp-lpass-clocks.o 9 obj-$(CONFIG_SND_SOC_QDSP6_AFE_CLOCKS) += q6afe-clocks.o 19 obj-$(CONFIG_SND_SOC_QDSP6_PRM_LPASS_CLOCKS) += q6prm-clocks.o
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/linux-master/drivers/clk/ingenic/ |
H A D | tcu.c | 3 * JZ47xx SoCs TCU clocks driver 55 struct clk_hw_onecell_data *clocks; member in struct:ingenic_tcu 271 struct clk_hw_onecell_data *clocks) 296 clocks->hws[idx] = &tcu_clk->hw; 382 tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT), 384 if (!tcu->clocks) { 389 tcu->clocks->num = TCU_CLK_COUNT; 394 tcu->clocks); 402 * We set EXT as the default parent clock for all the TCU clocks 268 ingenic_tcu_register_clock(struct ingenic_tcu *tcu, unsigned int idx, enum tcu_clk_parent parent, const struct ingenic_tcu_clk_info *info, struct clk_hw_onecell_data *clocks) argument [all...] |
/linux-master/include/trace/events/ |
H A D | fsi_master_gpio.h | 54 TP_PROTO(const struct fsi_master_gpio *master, int clocks), 55 TP_ARGS(master, clocks), 58 __field(int, clocks) 62 __entry->clocks = clocks; 65 __entry->master_idx, __entry->clocks
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/linux-master/drivers/clk/tegra/ |
H A D | clk-bpmp.c | 424 struct tegra_bpmp_clk_info *clocks; local 437 clocks = kcalloc(max_id + 1, sizeof(*clocks), GFP_KERNEL); 438 if (!clocks) 442 struct tegra_bpmp_clk_info *info = &clocks[count]; 469 *clocksp = clocks; 475 tegra_bpmp_clk_id_to_index(const struct tegra_bpmp_clk_info *clocks, argument 481 if (clocks[i].id == id) 488 tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks, argument 493 i = tegra_bpmp_clk_id_to_index(clocks, num_clock 502 tegra_bpmp_clk_register(struct tegra_bpmp *bpmp, const struct tegra_bpmp_clk_info *info, const struct tegra_bpmp_clk_info *clocks, unsigned int num_clocks) argument 678 struct tegra_bpmp_clk_info *clocks; local [all...] |
/linux-master/sound/soc/mediatek/mt8173/ |
H A D | mt8173-afe-pcm.c | 150 struct clk *clocks[MT8173_CLK_NUM]; member in struct:mt8173_afe_private 328 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], 330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], 351 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 352 afe_priv->clocks[MT8173_CLK_I2S3_B]); 365 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 366 afe_priv->clocks[MT8173_CLK_I2S3_B]); 378 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 380 afe_priv->clocks[MT8173_CLK_I2S3_B], 960 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_ [all...] |
/linux-master/drivers/clocksource/ |
H A D | ingenic-sysost.c | 3 * Ingenic XBurst SoCs SYSOST clocks driver 81 struct clk_hw_onecell_data *clocks; member in struct:ingenic_ost 272 struct clk_hw_onecell_data *clocks) 297 clocks->hws[idx] = &ost_clk->hw; 456 ost->clocks = kzalloc(struct_size(ost->clocks, hws, ost->soc_info->num_channels), 458 if (!ost->clocks) { 463 ost->clocks->num = ost->soc_info->num_channels; 465 for (i = 0; i < ost->clocks->num; i++) { 466 ret = ingenic_ost_register_clock(ost, i, &x1000_ost_clk_info[i], ost->clocks); 270 ingenic_ost_register_clock(struct ingenic_ost *ost, unsigned int idx, const struct ingenic_ost_clk_info *info, struct clk_hw_onecell_data *clocks) argument [all...] |
/linux-master/drivers/interconnect/ |
H A D | icc-clk.c | 19 struct icc_clk_node clocks[] __counted_by(num_clocks); 91 qp = devm_kzalloc(dev, struct_size(qp, clocks, num_clocks), GFP_KERNEL); 109 qp->clocks[i].clk = data[i].clk; 118 node->data = &qp->clocks[i]; 164 struct icc_clk_node *qn = &qp->clocks[i]; 173 MODULE_DESCRIPTION("Interconnect wrapper for clocks");
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/linux-master/sound/soc/codecs/ |
H A D | tlv320aic32x4.c | 721 static struct clk_bulk_data clocks[] = { local 729 ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks); 788 if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0) 791 clk_set_rate(clocks[0].clk, 794 clk_set_rate(clocks[1].clk, 797 clk_set_rate(clocks[2].clk, 802 clk_set_rate(clocks[3].clk, 805 clk_set_rate(clocks[4].clk, 810 clk_set_rate(clocks[ 889 static struct clk_bulk_data clocks[] = { local 914 clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks); local 1005 static struct clk_bulk_data clocks[] = { local 1154 static struct clk_bulk_data clocks[] = { local [all...] |
/linux-master/drivers/ata/ |
H A D | pata_atp867x.c | 142 unsigned char clocks = clk; local 149 clocks++; 151 switch (clocks) { 153 clocks = 1; 162 clocks = 7; /* 12 clk */ 166 clocks = 0; 171 return clocks << ATP867X_IO_PIOSPD_ACTIVE_SHIFT; 177 unsigned char clocks = clk; local 179 switch (clocks) { 181 clocks [all...] |
H A D | pata_hpt366.c | 122 struct hpt_clock *clocks = ap->host->private_data; local 124 while (clocks->xfer_mode) { 125 if (clocks->xfer_mode == speed) 126 return clocks->timing; 127 clocks++;
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/linux-master/drivers/clk/hisilicon/ |
H A D | clk.h | 142 struct clk **clocks = data->clk_data.clks; \ 146 if (clocks[id]) \ 147 clk_unregister_##type(clocks[id]); \
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/linux-master/drivers/clk/renesas/ |
H A D | r9a06g032-clocks.c | 111 * @ffc: substructure for fixed-factor clocks 629 * These are not hardware clocks, but are needed to handle the special 699 static void clk_rdesc_set(struct r9a06g032_priv *clocks, argument 702 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 713 static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb) argument 715 u32 __iomem *reg = clocks->reg + (rb.reg * 4); 728 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_gate 770 while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i++, 815 r9a06g032_clk_gate_set(struct r9a06g032_priv *clocks, argument 822 spin_lock_irqsave(&clocks 877 r9a06g032_register_gate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 920 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_div 1048 r9a06g032_register_div(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 1101 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_bitsel 1133 r9a06g032_register_bitsel(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc) argument 1171 struct r9a06g032_priv *clocks; member in struct:r9a06g032_clk_dualgate 1223 r9a06g032_register_dualgate(struct r9a06g032_priv *clocks, const char *parent_name, const struct r9a06g032_clkdesc *desc, struct regbit sel) argument 1273 r9a06g032_init_h2mode(struct r9a06g032_priv *clocks) argument 1299 struct r9a06g032_priv *clocks; local [all...] |
/linux-master/drivers/clk/ti/ |
H A D | adpll.c | 170 struct ti_adpll_clock *clocks; member in struct:ti_adpll_data 207 d->clocks[index].clk = clock; 208 d->clocks[index].unregister = unregister; 220 d->clocks[index].cl = cl; 642 d->clocks[TI_ADPLL_N2].clk, 651 d->clocks[TI_ADPLL_DCO].clk, 661 d->clocks[TI_ADPLL_M2].clk, 669 d->clocks[TI_ADPLL_DIV2].clk, 670 d->clocks[TI_ADPLL_BYPASS].clk); 676 "clkout2", d->clocks[TI_ADPLL_M [all...] |
/linux-master/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_lvds.c | 76 struct clk *dotclkin[2]; /* External DU clocks */ 77 } clocks; member in struct:rcar_lvds 278 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, 280 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, 282 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, 828 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false); 829 if (IS_ERR(lvds->clocks.mod)) 830 return PTR_ERR(lvds->clocks.mod); 838 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); 839 if (IS_ERR(lvds->clocks [all...] |
/linux-master/drivers/gpu/drm/tegra/ |
H A D | gr3d.c | 45 struct clk_bulk_data *clocks; member in struct:gr3d 319 * for the clocks. 325 clk = gr3d->clocks[0].clk; 328 if (WARN_ON(!gr3d->clocks[i].id)) 331 if (!strcmp(gr3d->clocks[i].id, name)) { 332 clk = gr3d->clocks[i].clk; 364 * tegra_powergate_sequence_power_up() leaves clocks enabled, 447 err = devm_clk_bulk_get_all(dev, &gr3d->clocks); 455 dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); 575 clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); [all...] |
/linux-master/drivers/media/platform/samsung/exynos4-is/ |
H A D | fimc-is.c | 70 if (IS_ERR(is->clocks[i])) 72 clk_put(is->clocks[i]); 73 is->clocks[i] = ERR_PTR(-EINVAL); 82 is->clocks[i] = ERR_PTR(-EINVAL); 85 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]); 86 if (IS_ERR(is->clocks[i])) { 87 ret = PTR_ERR(is->clocks[i]); 104 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200], 105 is->clocks[ISS_CLK_ACLK200_DIV]); 109 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUIS [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/ |
H A D | amd_powerplay.c | 1062 struct amd_pp_clock_info *clocks) 1087 clocks->min_engine_clock = hw_clocks.min_eng_clk; 1088 clocks->max_engine_clock = hw_clocks.max_eng_clk; 1089 clocks->min_memory_clock = hw_clocks.min_mem_clk; 1090 clocks->max_memory_clock = hw_clocks.max_mem_clk; 1091 clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth; 1092 clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth; 1094 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk; 1095 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk; 1098 clocks 1061 pp_get_current_clocks(void *handle, struct amd_pp_clock_info *clocks) argument 1109 pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) argument 1122 pp_get_clock_by_type_with_latency(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) argument 1134 pp_get_clock_by_type_with_voltage(void *handle, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) argument 1169 pp_get_display_mode_validation_clocks(void *handle, struct amd_pp_simple_clock_info *clocks) argument [all...] |
/linux-master/drivers/i2c/busses/ |
H A D | i2c-mt65xx.c | 94 * @I2C_MT65XX_CLK_MAX: Number of supported clocks 295 struct clk_bulk_data clocks[I2C_MT65XX_CLK_MAX]; /* clocks for i2c */ member in struct:mtk_i2c 1248 ret = clk_bulk_enable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1302 clk_bulk_disable(I2C_MT65XX_CLK_MAX, i2c->clocks); 1426 i2c->clocks[i].id = i2c_mt65xx_clk_ids[i]; 1428 /* Get clocks one by one, some may be optional */ 1429 i2c->clocks[I2C_MT65XX_CLK_MAIN].clk = devm_clk_get(&pdev->dev, "main"); 1430 if (IS_ERR(i2c->clocks[I2C_MT65XX_CLK_MAIN].clk)) { 1432 return PTR_ERR(i2c->clocks[I2C_MT65XX_CLK_MAI [all...] |
/linux-master/drivers/irqchip/ |
H A D | irq-gic-pm.c | 16 const char *const *clocks; member in struct:gic_clk_data 94 chip_pm->clks[i].id = data->clocks[i]; 142 .clocks = gic400_clocks,
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | hardwaremanager.c | 398 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result); 409 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result); 429 int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks) argument 436 return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks); 442 struct pp_clock_levels_with_latency *clocks) 449 return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks); 455 struct pp_clock_levels_with_voltage *clocks) 462 return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks); 489 int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks) argument 496 return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks); 440 phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_latency *clocks) argument 453 phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct pp_clock_levels_with_voltage *clocks) argument [all...] |