1// SPDX-License-Identifier: GPL-2.0 2/* 3 * R-Car LVDS Encoder 4 * 5 * Copyright (C) 2013-2018 Renesas Electronics Corporation 6 * 7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 8 */ 9 10#include <linux/clk.h> 11#include <linux/delay.h> 12#include <linux/io.h> 13#include <linux/media-bus-format.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/of_device.h> 17#include <linux/of_graph.h> 18#include <linux/platform_device.h> 19#include <linux/pm_runtime.h> 20#include <linux/reset.h> 21#include <linux/slab.h> 22#include <linux/sys_soc.h> 23 24#include <drm/drm_atomic.h> 25#include <drm/drm_atomic_helper.h> 26#include <drm/drm_bridge.h> 27#include <drm/drm_of.h> 28#include <drm/drm_panel.h> 29#include <drm/drm_print.h> 30#include <drm/drm_probe_helper.h> 31 32#include "rcar_lvds.h" 33#include "rcar_lvds_regs.h" 34 35struct rcar_lvds; 36 37/* Keep in sync with the LVDCR0.LVMD hardware register values. */ 38enum rcar_lvds_mode { 39 RCAR_LVDS_MODE_JEIDA = 0, 40 RCAR_LVDS_MODE_MIRROR = 1, 41 RCAR_LVDS_MODE_VESA = 4, 42}; 43 44enum rcar_lvds_link_type { 45 RCAR_LVDS_SINGLE_LINK = 0, 46 RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1, 47 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2, 48}; 49 50#define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */ 51#define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */ 52#define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */ 53#define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */ 54#define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */ 55 56struct rcar_lvds_device_info { 57 unsigned int gen; 58 unsigned int quirks; 59 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq); 60}; 61 62struct rcar_lvds { 63 struct device *dev; 64 const struct rcar_lvds_device_info *info; 65 struct reset_control *rstc; 66 67 struct drm_bridge bridge; 68 69 struct drm_bridge *next_bridge; 70 struct drm_panel *panel; 71 72 void __iomem *mmio; 73 struct { 74 struct clk *mod; /* CPG module clock */ 75 struct clk *extal; /* External clock */ 76 struct clk *dotclkin[2]; /* External DU clocks */ 77 } clocks; 78 79 struct drm_bridge *companion; 80 enum rcar_lvds_link_type link_type; 81}; 82 83#define bridge_to_rcar_lvds(b) \ 84 container_of(b, struct rcar_lvds, bridge) 85 86static u32 rcar_lvds_read(struct rcar_lvds *lvds, u32 reg) 87{ 88 return ioread32(lvds->mmio + reg); 89} 90 91static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data) 92{ 93 iowrite32(data, lvds->mmio + reg); 94} 95 96/* ----------------------------------------------------------------------------- 97 * PLL Setup 98 */ 99 100static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq) 101{ 102 u32 val; 103 104 if (freq < 39000000) 105 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M; 106 else if (freq < 61000000) 107 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M; 108 else if (freq < 121000000) 109 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M; 110 else 111 val = LVDPLLCR_PLLDLYCNT_150M; 112 113 rcar_lvds_write(lvds, LVDPLLCR, val); 114} 115 116static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq) 117{ 118 u32 val; 119 120 if (freq < 42000000) 121 val = LVDPLLCR_PLLDIVCNT_42M; 122 else if (freq < 85000000) 123 val = LVDPLLCR_PLLDIVCNT_85M; 124 else if (freq < 128000000) 125 val = LVDPLLCR_PLLDIVCNT_128M; 126 else 127 val = LVDPLLCR_PLLDIVCNT_148M; 128 129 rcar_lvds_write(lvds, LVDPLLCR, val); 130} 131 132struct pll_info { 133 unsigned long diff; 134 unsigned int pll_m; 135 unsigned int pll_n; 136 unsigned int pll_e; 137 unsigned int div; 138 u32 clksel; 139}; 140 141static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk, 142 unsigned long target, struct pll_info *pll, 143 u32 clksel, bool dot_clock_only) 144{ 145 unsigned int div7 = dot_clock_only ? 1 : 7; 146 unsigned long output; 147 unsigned long fin; 148 unsigned int m_min; 149 unsigned int m_max; 150 unsigned int m; 151 int error; 152 153 if (!clk) 154 return; 155 156 /* 157 * The LVDS PLL is made of a pre-divider and a multiplier (strangely 158 * enough called M and N respectively), followed by a post-divider E. 159 * 160 * ,-----. ,-----. ,-----. ,-----. 161 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout 162 * `-----' ,-> | | `-----' | `-----' 163 * | `-----' | 164 * | ,-----. | 165 * `-------- | 1/N | <-------' 166 * `-----' 167 * 168 * The clock output by the PLL is then further divided by a programmable 169 * divider DIV to achieve the desired target frequency. Finally, an 170 * optional fixed /7 divider is used to convert the bit clock to a pixel 171 * clock (as LVDS transmits 7 bits per lane per clock sample). 172 * 173 * ,-------. ,-----. |\ 174 * Fout --> | 1/DIV | --> | 1/7 | --> | | 175 * `-------' | `-----' | | --> dot clock 176 * `------------> | | 177 * |/ 178 * 179 * The /7 divider is optional, it is enabled when the LVDS PLL is used 180 * to drive the LVDS encoder, and disabled when used to generate a dot 181 * clock for the DU RGB output, without using the LVDS encoder. 182 * 183 * The PLL allowed input frequency range is 12 MHz to 192 MHz. 184 */ 185 186 fin = clk_get_rate(clk); 187 if (fin < 12000000 || fin > 192000000) 188 return; 189 190 /* 191 * The comparison frequency range is 12 MHz to 24 MHz, which limits the 192 * allowed values for the pre-divider M (normal range 1-8). 193 * 194 * Fpfd = Fin / M 195 */ 196 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000)); 197 m_max = min_t(unsigned int, 8, fin / 12000000); 198 199 for (m = m_min; m <= m_max; ++m) { 200 unsigned long fpfd; 201 unsigned int n_min; 202 unsigned int n_max; 203 unsigned int n; 204 205 /* 206 * The VCO operating range is 900 Mhz to 1800 MHz, which limits 207 * the allowed values for the multiplier N (normal range 208 * 60-120). 209 * 210 * Fvco = Fin * N / M 211 */ 212 fpfd = fin / m; 213 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd)); 214 n_max = min_t(unsigned int, 120, 1800000000 / fpfd); 215 216 for (n = n_min; n < n_max; ++n) { 217 unsigned long fvco; 218 unsigned int e_min; 219 unsigned int e; 220 221 /* 222 * The output frequency is limited to 1039.5 MHz, 223 * limiting again the allowed values for the 224 * post-divider E (normal value 1, 2 or 4). 225 * 226 * Fout = Fvco / E 227 */ 228 fvco = fpfd * n; 229 e_min = fvco > 1039500000 ? 1 : 0; 230 231 for (e = e_min; e < 3; ++e) { 232 unsigned long fout; 233 unsigned long diff; 234 unsigned int div; 235 236 /* 237 * Finally we have a programable divider after 238 * the PLL, followed by a an optional fixed /7 239 * divider. 240 */ 241 fout = fvco / (1 << e) / div7; 242 div = max(1UL, DIV_ROUND_CLOSEST(fout, target)); 243 diff = abs(fout / div - target); 244 245 if (diff < pll->diff) { 246 pll->diff = diff; 247 pll->pll_m = m; 248 pll->pll_n = n; 249 pll->pll_e = e; 250 pll->div = div; 251 pll->clksel = clksel; 252 253 if (diff == 0) 254 goto done; 255 } 256 } 257 } 258 } 259 260done: 261 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e) 262 / div7 / pll->div; 263 error = (long)(output - target) * 10000 / (long)target; 264 265 dev_dbg(lvds->dev, 266 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n", 267 clk, fin, output, target, error / 100, 268 error < 0 ? -error % 100 : error % 100, 269 pll->pll_m, pll->pll_n, pll->pll_e, pll->div); 270} 271 272static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, 273 unsigned int freq, bool dot_clock_only) 274{ 275 struct pll_info pll = { .diff = (unsigned long)-1 }; 276 u32 lvdpllcr; 277 278 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll, 279 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only); 280 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll, 281 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only); 282 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll, 283 LVDPLLCR_CKSEL_EXTAL, dot_clock_only); 284 285 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT 286 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1); 287 288 if (pll.pll_e > 0) 289 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL 290 | LVDPLLCR_PLLE(pll.pll_e - 1); 291 292 if (dot_clock_only) 293 lvdpllcr |= LVDPLLCR_OCKSEL; 294 295 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr); 296 297 if (pll.div > 1) 298 /* 299 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the 300 * divisor reset. 301 */ 302 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL | 303 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1)); 304 else 305 rcar_lvds_write(lvds, LVDDIV, 0); 306} 307 308/* ----------------------------------------------------------------------------- 309 * Enable/disable 310 */ 311 312static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds, 313 const struct drm_connector *connector) 314{ 315 const struct drm_display_info *info; 316 enum rcar_lvds_mode mode; 317 318 /* 319 * There is no API yet to retrieve LVDS mode from a bridge, only panels 320 * are supported. 321 */ 322 if (!lvds->panel) 323 return RCAR_LVDS_MODE_JEIDA; 324 325 info = &connector->display_info; 326 if (!info->num_bus_formats || !info->bus_formats) { 327 dev_warn(lvds->dev, 328 "no LVDS bus format reported, using JEIDA\n"); 329 return RCAR_LVDS_MODE_JEIDA; 330 } 331 332 switch (info->bus_formats[0]) { 333 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 334 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 335 mode = RCAR_LVDS_MODE_JEIDA; 336 break; 337 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 338 mode = RCAR_LVDS_MODE_VESA; 339 break; 340 default: 341 dev_warn(lvds->dev, 342 "unsupported LVDS bus format 0x%04x, using JEIDA\n", 343 info->bus_formats[0]); 344 return RCAR_LVDS_MODE_JEIDA; 345 } 346 347 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB) 348 mode |= RCAR_LVDS_MODE_MIRROR; 349 350 return mode; 351} 352 353static void rcar_lvds_enable(struct drm_bridge *bridge, 354 struct drm_atomic_state *state, 355 struct drm_crtc *crtc, 356 struct drm_connector *connector) 357{ 358 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 359 u32 lvdhcr; 360 u32 lvdcr0; 361 int ret; 362 363 ret = pm_runtime_resume_and_get(lvds->dev); 364 if (ret) 365 return; 366 367 /* Enable the companion LVDS encoder in dual-link mode. */ 368 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion) 369 rcar_lvds_enable(lvds->companion, state, crtc, connector); 370 371 /* 372 * Hardcode the channels and control signals routing for now. 373 * 374 * HSYNC -> CTRL0 375 * VSYNC -> CTRL1 376 * DISP -> CTRL2 377 * 0 -> CTRL3 378 */ 379 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO | 380 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC | 381 LVDCTRCR_CTR0SEL_HSYNC); 382 383 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES) 384 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3) 385 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1); 386 else 387 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1) 388 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3); 389 390 rcar_lvds_write(lvds, LVDCHCR, lvdhcr); 391 392 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) { 393 u32 lvdstripe = 0; 394 395 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) { 396 /* 397 * By default we generate even pixels from the primary 398 * encoder and odd pixels from the companion encoder. 399 * Swap pixels around if the sink requires odd pixels 400 * from the primary encoder and even pixels from the 401 * companion encoder. 402 */ 403 bool swap_pixels = lvds->link_type == 404 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS; 405 406 /* 407 * Configure vertical stripe since we are dealing with 408 * an LVDS dual-link connection. 409 * 410 * ST_SWAP is reserved for the companion encoder, only 411 * set it in the primary encoder. 412 */ 413 lvdstripe = LVDSTRIPE_ST_ON 414 | (lvds->companion && swap_pixels ? 415 LVDSTRIPE_ST_SWAP : 0); 416 } 417 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe); 418 } 419 420 /* 421 * PLL clock configuration on all instances but the companion in 422 * dual-link mode. 423 * 424 * The extended PLL has been turned on by an explicit call to 425 * rcar_lvds_pclk_enable() from the DU driver. 426 */ 427 if ((lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) && 428 !(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { 429 const struct drm_crtc_state *crtc_state = 430 drm_atomic_get_new_crtc_state(state, crtc); 431 const struct drm_display_mode *mode = 432 &crtc_state->adjusted_mode; 433 434 lvds->info->pll_setup(lvds, mode->clock * 1000); 435 } 436 437 /* Set the LVDS mode and select the input. */ 438 lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT; 439 440 if (lvds->bridge.encoder) { 441 if (drm_crtc_index(crtc) == 2) 442 lvdcr0 |= LVDCR0_DUSEL; 443 } 444 445 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 446 447 /* Turn all the channels on. */ 448 rcar_lvds_write(lvds, LVDCR1, 449 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | 450 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY); 451 452 if (lvds->info->gen < 3) { 453 /* Enable LVDS operation and turn the bias circuitry on. */ 454 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN; 455 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 456 } 457 458 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { 459 /* 460 * Turn the PLL on (simple PLL only, extended PLL is fully 461 * controlled through LVDPLLCR). 462 */ 463 lvdcr0 |= LVDCR0_PLLON; 464 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 465 } 466 467 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { 468 /* Set LVDS normal mode. */ 469 lvdcr0 |= LVDCR0_PWD; 470 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 471 } 472 473 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { 474 /* 475 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be 476 * set at the same time, so don't write the register yet. 477 */ 478 lvdcr0 |= LVDCR0_LVEN; 479 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD)) 480 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 481 } 482 483 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { 484 /* Wait for the PLL startup delay (simple PLL only). */ 485 usleep_range(100, 150); 486 } 487 488 /* Turn the output on. */ 489 lvdcr0 |= LVDCR0_LVRES; 490 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 491} 492 493static void rcar_lvds_disable(struct drm_bridge *bridge) 494{ 495 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 496 u32 lvdcr0; 497 498 /* 499 * Clear the LVDCR0 bits in the order specified by the hardware 500 * documentation, ending with a write of 0 to the full register to 501 * clear all remaining bits. 502 */ 503 lvdcr0 = rcar_lvds_read(lvds, LVDCR0); 504 505 lvdcr0 &= ~LVDCR0_LVRES; 506 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 507 508 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) { 509 lvdcr0 &= ~LVDCR0_LVEN; 510 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 511 } 512 513 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) { 514 lvdcr0 &= ~LVDCR0_PWD; 515 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 516 } 517 518 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) { 519 lvdcr0 &= ~LVDCR0_PLLON; 520 rcar_lvds_write(lvds, LVDCR0, lvdcr0); 521 } 522 523 rcar_lvds_write(lvds, LVDCR0, 0); 524 rcar_lvds_write(lvds, LVDCR1, 0); 525 526 /* The extended PLL is turned off in rcar_lvds_pclk_disable(). */ 527 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) 528 rcar_lvds_write(lvds, LVDPLLCR, 0); 529 530 /* Disable the companion LVDS encoder in dual-link mode. */ 531 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion) 532 rcar_lvds_disable(lvds->companion); 533 534 pm_runtime_put_sync(lvds->dev); 535} 536 537/* ----------------------------------------------------------------------------- 538 * Clock - D3/E3 only 539 */ 540 541int rcar_lvds_pclk_enable(struct drm_bridge *bridge, unsigned long freq, 542 bool dot_clk_only) 543{ 544 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 545 int ret; 546 547 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))) 548 return -ENODEV; 549 550 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq); 551 552 ret = pm_runtime_resume_and_get(lvds->dev); 553 if (ret) 554 return ret; 555 556 rcar_lvds_pll_setup_d3_e3(lvds, freq, dot_clk_only); 557 558 return 0; 559} 560EXPORT_SYMBOL_GPL(rcar_lvds_pclk_enable); 561 562void rcar_lvds_pclk_disable(struct drm_bridge *bridge, bool dot_clk_only) 563{ 564 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 565 566 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))) 567 return; 568 569 dev_dbg(lvds->dev, "disabling LVDS PLL\n"); 570 571 if (!dot_clk_only) 572 rcar_lvds_disable(bridge); 573 574 rcar_lvds_write(lvds, LVDPLLCR, 0); 575 576 pm_runtime_put_sync(lvds->dev); 577} 578EXPORT_SYMBOL_GPL(rcar_lvds_pclk_disable); 579 580/* ----------------------------------------------------------------------------- 581 * Bridge 582 */ 583 584static void rcar_lvds_atomic_enable(struct drm_bridge *bridge, 585 struct drm_bridge_state *old_bridge_state) 586{ 587 struct drm_atomic_state *state = old_bridge_state->base.state; 588 struct drm_connector *connector; 589 struct drm_crtc *crtc; 590 591 connector = drm_atomic_get_new_connector_for_encoder(state, 592 bridge->encoder); 593 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 594 595 rcar_lvds_enable(bridge, state, crtc, connector); 596} 597 598static void rcar_lvds_atomic_disable(struct drm_bridge *bridge, 599 struct drm_bridge_state *old_bridge_state) 600{ 601 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 602 603 /* 604 * For D3 and E3, disabling the LVDS encoder before the DU would stall 605 * the DU, causing a vblank wait timeout when stopping the DU. This has 606 * been traced to clearing the LVEN bit, but the exact reason is 607 * unknown. Keep the encoder enabled, it will be disabled by an explicit 608 * call to rcar_lvds_pclk_disable() from the DU driver. 609 * 610 * We could clear the LVRES bit already to disable the LVDS output, but 611 * that's likely pointless. 612 */ 613 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL) 614 return; 615 616 rcar_lvds_disable(bridge); 617} 618 619static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge, 620 const struct drm_display_mode *mode, 621 struct drm_display_mode *adjusted_mode) 622{ 623 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 624 int min_freq; 625 626 /* 627 * The internal LVDS encoder has a restricted clock frequency operating 628 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to 629 * 148.5MHz on all other platforms. Clamp the clock accordingly. 630 */ 631 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000; 632 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500); 633 634 return true; 635} 636 637static int rcar_lvds_attach(struct drm_bridge *bridge, 638 enum drm_bridge_attach_flags flags) 639{ 640 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 641 642 if (!lvds->next_bridge) 643 return 0; 644 645 return drm_bridge_attach(bridge->encoder, lvds->next_bridge, bridge, 646 flags); 647} 648 649static const struct drm_bridge_funcs rcar_lvds_bridge_ops = { 650 .attach = rcar_lvds_attach, 651 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 652 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 653 .atomic_reset = drm_atomic_helper_bridge_reset, 654 .atomic_enable = rcar_lvds_atomic_enable, 655 .atomic_disable = rcar_lvds_atomic_disable, 656 .mode_fixup = rcar_lvds_mode_fixup, 657}; 658 659bool rcar_lvds_dual_link(struct drm_bridge *bridge) 660{ 661 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 662 663 return lvds->link_type != RCAR_LVDS_SINGLE_LINK; 664} 665EXPORT_SYMBOL_GPL(rcar_lvds_dual_link); 666 667bool rcar_lvds_is_connected(struct drm_bridge *bridge) 668{ 669 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge); 670 671 return lvds->next_bridge != NULL; 672} 673EXPORT_SYMBOL_GPL(rcar_lvds_is_connected); 674 675/* ----------------------------------------------------------------------------- 676 * Probe & Remove 677 */ 678 679static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds) 680{ 681 const struct of_device_id *match; 682 struct device_node *companion; 683 struct device_node *port0, *port1; 684 struct rcar_lvds *companion_lvds; 685 struct device *dev = lvds->dev; 686 int dual_link; 687 int ret = 0; 688 689 /* Locate the companion LVDS encoder for dual-link operation, if any. */ 690 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0); 691 if (!companion) 692 return 0; 693 694 /* 695 * Sanity check: the companion encoder must have the same compatible 696 * string. 697 */ 698 match = of_match_device(dev->driver->of_match_table, dev); 699 if (!of_device_is_compatible(companion, match->compatible)) { 700 dev_err(dev, "Companion LVDS encoder is invalid\n"); 701 ret = -ENXIO; 702 goto done; 703 } 704 705 /* 706 * We need to work out if the sink is expecting us to function in 707 * dual-link mode. We do this by looking at the DT port nodes we are 708 * connected to, if they are marked as expecting even pixels and 709 * odd pixels than we need to enable vertical stripe output. 710 */ 711 port0 = of_graph_get_port_by_id(dev->of_node, 1); 712 port1 = of_graph_get_port_by_id(companion, 1); 713 dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1); 714 of_node_put(port0); 715 of_node_put(port1); 716 717 switch (dual_link) { 718 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: 719 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS; 720 break; 721 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: 722 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS; 723 break; 724 default: 725 /* 726 * Early dual-link bridge specific implementations populate the 727 * timings field of drm_bridge. If the flag is set, we assume 728 * that we are expected to generate even pixels from the primary 729 * encoder, and odd pixels from the companion encoder. 730 */ 731 if (lvds->next_bridge->timings && 732 lvds->next_bridge->timings->dual_link) 733 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS; 734 else 735 lvds->link_type = RCAR_LVDS_SINGLE_LINK; 736 } 737 738 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) { 739 dev_dbg(dev, "Single-link configuration detected\n"); 740 goto done; 741 } 742 743 lvds->companion = of_drm_find_bridge(companion); 744 if (!lvds->companion) { 745 ret = -EPROBE_DEFER; 746 goto done; 747 } 748 749 dev_dbg(dev, 750 "Dual-link configuration detected (companion encoder %pOF)\n", 751 companion); 752 753 if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) 754 dev_dbg(dev, "Data swapping required\n"); 755 756 /* 757 * FIXME: We should not be messing with the companion encoder private 758 * data from the primary encoder, we should rather let the companion 759 * encoder work things out on its own. However, the companion encoder 760 * doesn't hold a reference to the primary encoder, and 761 * drm_of_lvds_get_dual_link_pixel_order needs to be given references 762 * to the output ports of both encoders, therefore leave it like this 763 * for the time being. 764 */ 765 companion_lvds = bridge_to_rcar_lvds(lvds->companion); 766 companion_lvds->link_type = lvds->link_type; 767 768done: 769 of_node_put(companion); 770 771 return ret; 772} 773 774static int rcar_lvds_parse_dt(struct rcar_lvds *lvds) 775{ 776 int ret; 777 778 ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0, 779 &lvds->panel, &lvds->next_bridge); 780 if (ret) 781 goto done; 782 783 if (lvds->panel) { 784 lvds->next_bridge = devm_drm_panel_bridge_add(lvds->dev, 785 lvds->panel); 786 if (IS_ERR_OR_NULL(lvds->next_bridge)) { 787 ret = -EINVAL; 788 goto done; 789 } 790 } 791 792 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) 793 ret = rcar_lvds_parse_dt_companion(lvds); 794 795done: 796 /* 797 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be 798 * used for the DPAD output even when the LVDS output is not connected. 799 * Don't fail probe in that case as the DU will need the bridge to 800 * control the clock. 801 */ 802 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL) 803 return ret == -ENODEV ? 0 : ret; 804 805 return ret; 806} 807 808static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name, 809 bool optional) 810{ 811 struct clk *clk; 812 813 clk = devm_clk_get(lvds->dev, name); 814 if (!IS_ERR(clk)) 815 return clk; 816 817 if (PTR_ERR(clk) == -ENOENT && optional) 818 return NULL; 819 820 dev_err_probe(lvds->dev, PTR_ERR(clk), "failed to get %s clock\n", 821 name ? name : "module"); 822 823 return clk; 824} 825 826static int rcar_lvds_get_clocks(struct rcar_lvds *lvds) 827{ 828 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false); 829 if (IS_ERR(lvds->clocks.mod)) 830 return PTR_ERR(lvds->clocks.mod); 831 832 /* 833 * LVDS encoders without an extended PLL have no external clock inputs. 834 */ 835 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) 836 return 0; 837 838 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true); 839 if (IS_ERR(lvds->clocks.extal)) 840 return PTR_ERR(lvds->clocks.extal); 841 842 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true); 843 if (IS_ERR(lvds->clocks.dotclkin[0])) 844 return PTR_ERR(lvds->clocks.dotclkin[0]); 845 846 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true); 847 if (IS_ERR(lvds->clocks.dotclkin[1])) 848 return PTR_ERR(lvds->clocks.dotclkin[1]); 849 850 /* At least one input to the PLL must be available. */ 851 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] && 852 !lvds->clocks.dotclkin[1]) { 853 dev_err(lvds->dev, 854 "no input clock (extal, dclkin.0 or dclkin.1)\n"); 855 return -EINVAL; 856 } 857 858 return 0; 859} 860 861static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = { 862 .gen = 2, 863 .quirks = RCAR_LVDS_QUIRK_LANES, 864 .pll_setup = rcar_lvds_pll_setup_gen2, 865}; 866 867static const struct soc_device_attribute lvds_quirk_matches[] = { 868 { 869 .soc_id = "r8a7790", .revision = "ES1.*", 870 .data = &rcar_lvds_r8a7790es1_info, 871 }, 872 { /* sentinel */ } 873}; 874 875static int rcar_lvds_probe(struct platform_device *pdev) 876{ 877 const struct soc_device_attribute *attr; 878 struct rcar_lvds *lvds; 879 int ret; 880 881 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); 882 if (lvds == NULL) 883 return -ENOMEM; 884 885 platform_set_drvdata(pdev, lvds); 886 887 lvds->dev = &pdev->dev; 888 lvds->info = of_device_get_match_data(&pdev->dev); 889 890 attr = soc_device_match(lvds_quirk_matches); 891 if (attr) 892 lvds->info = attr->data; 893 894 ret = rcar_lvds_parse_dt(lvds); 895 if (ret < 0) 896 return ret; 897 898 lvds->bridge.funcs = &rcar_lvds_bridge_ops; 899 lvds->bridge.of_node = pdev->dev.of_node; 900 901 lvds->mmio = devm_platform_ioremap_resource(pdev, 0); 902 if (IS_ERR(lvds->mmio)) 903 return PTR_ERR(lvds->mmio); 904 905 ret = rcar_lvds_get_clocks(lvds); 906 if (ret < 0) 907 return ret; 908 909 lvds->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 910 if (IS_ERR(lvds->rstc)) 911 return dev_err_probe(&pdev->dev, PTR_ERR(lvds->rstc), 912 "failed to get cpg reset\n"); 913 914 pm_runtime_enable(&pdev->dev); 915 916 drm_bridge_add(&lvds->bridge); 917 918 return 0; 919} 920 921static void rcar_lvds_remove(struct platform_device *pdev) 922{ 923 struct rcar_lvds *lvds = platform_get_drvdata(pdev); 924 925 drm_bridge_remove(&lvds->bridge); 926 927 pm_runtime_disable(&pdev->dev); 928} 929 930static const struct rcar_lvds_device_info rcar_lvds_gen2_info = { 931 .gen = 2, 932 .pll_setup = rcar_lvds_pll_setup_gen2, 933}; 934 935static const struct rcar_lvds_device_info rcar_lvds_gen3_info = { 936 .gen = 3, 937 .quirks = RCAR_LVDS_QUIRK_PWD, 938 .pll_setup = rcar_lvds_pll_setup_gen3, 939}; 940 941static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = { 942 .gen = 3, 943 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN, 944 .pll_setup = rcar_lvds_pll_setup_gen2, 945}; 946 947static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = { 948 .gen = 3, 949 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL 950 | RCAR_LVDS_QUIRK_DUAL_LINK, 951}; 952 953static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = { 954 .gen = 3, 955 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD 956 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK, 957}; 958 959static const struct of_device_id rcar_lvds_of_table[] = { 960 { .compatible = "renesas,r8a7742-lvds", .data = &rcar_lvds_gen2_info }, 961 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info }, 962 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info }, 963 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info }, 964 { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info }, 965 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info }, 966 { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info }, 967 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info }, 968 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info }, 969 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info }, 970 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info }, 971 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info }, 972 { .compatible = "renesas,r8a77961-lvds", .data = &rcar_lvds_gen3_info }, 973 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info }, 974 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info }, 975 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info }, 976 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info }, 977 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info }, 978 { } 979}; 980 981MODULE_DEVICE_TABLE(of, rcar_lvds_of_table); 982 983static int rcar_lvds_runtime_suspend(struct device *dev) 984{ 985 struct rcar_lvds *lvds = dev_get_drvdata(dev); 986 987 clk_disable_unprepare(lvds->clocks.mod); 988 989 reset_control_assert(lvds->rstc); 990 991 return 0; 992} 993 994static int rcar_lvds_runtime_resume(struct device *dev) 995{ 996 struct rcar_lvds *lvds = dev_get_drvdata(dev); 997 int ret; 998 999 ret = reset_control_deassert(lvds->rstc); 1000 if (ret) 1001 return ret; 1002 1003 ret = clk_prepare_enable(lvds->clocks.mod); 1004 if (ret < 0) 1005 goto err_reset_assert; 1006 1007 return 0; 1008 1009err_reset_assert: 1010 reset_control_assert(lvds->rstc); 1011 1012 return ret; 1013} 1014 1015static const struct dev_pm_ops rcar_lvds_pm_ops = { 1016 SET_RUNTIME_PM_OPS(rcar_lvds_runtime_suspend, rcar_lvds_runtime_resume, NULL) 1017}; 1018 1019static struct platform_driver rcar_lvds_platform_driver = { 1020 .probe = rcar_lvds_probe, 1021 .remove_new = rcar_lvds_remove, 1022 .driver = { 1023 .name = "rcar-lvds", 1024 .pm = &rcar_lvds_pm_ops, 1025 .of_match_table = rcar_lvds_of_table, 1026 }, 1027}; 1028 1029module_platform_driver(rcar_lvds_platform_driver); 1030 1031MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>"); 1032MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver"); 1033MODULE_LICENSE("GPL"); 1034