| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_opp.h | 45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
87 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
102 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
103 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
104 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
105 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
106 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABL
288 uint32_t FMT_BIT_DEPTH_CONTROL; member in struct:dce_opp_registers
[all...] |
| H A D | dce_opp.c | 109 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
118 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
124 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
134 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
153 /* DCE6 has no FMT_TRUNCATE_MODE bit in FMT_BIT_DEPTH_CONTROL reg */
156 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
163 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
168 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
177 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL,
204 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
[all...] |
| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_opp.c | 54 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
65 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
122 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
|
| H A D | dcn10_opp.h | 37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
54 uint32_t FMT_BIT_DEPTH_CONTROL; \
|
| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dce_v11_0.c | 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
583 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_E
[all...] |
| H A D | dce_v10_0.c | 537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_E
[all...] |
| H A D | sid.h | 2104 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
|
| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | cikd.h | 987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
|
| H A D | r600d.h | 1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
|
| H A D | evergreend.h | 1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
|
| H A D | r600.c | 346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
|
| H A D | evergreen.c | 1345 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
|
| H A D | cik.c | 8784 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
|
| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 535 SRI_ARR(FMT_BIT_DEPTH_CONTROL, FMT, id), SRI_ARR(FMT_CONTROL, FMT, id), \
|