| /linux-master/include/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 35 #define CLK_TOP_SYSPLL1_D2 25 macro
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| H A D | mt7622-clk.h | 31 #define CLK_TOP_SYSPLL1_D2 19 macro
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| H A D | mt6797-clk.h | 47 #define CLK_TOP_SYSPLL1_D2 37 macro
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| H A D | mt6765-clk.h | 37 #define CLK_TOP_SYSPLL1_D2 2 macro
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| H A D | mt8173-clk.h | 54 #define CLK_TOP_SYSPLL1_D2 44 macro
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| H A D | mediatek,mt6795-clk.h | 52 #define CLK_TOP_SYSPLL1_D2 41 macro
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| H A D | mt2701-clk.h | 16 #define CLK_TOP_SYSPLL1_D2 6 macro
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| H A D | mt2712-clk.h | 37 #define CLK_TOP_SYSPLL1_D2 6 macro
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| H A D | mediatek,mt8365-clk.h | 17 #define CLK_TOP_SYSPLL1_D2 7 macro
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| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt7629-clk.h | 35 #define CLK_TOP_SYSPLL1_D2 25 macro
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| H A D | mt7622-clk.h | 31 #define CLK_TOP_SYSPLL1_D2 19 macro
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| H A D | mt6797-clk.h | 47 #define CLK_TOP_SYSPLL1_D2 37 macro
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| H A D | mt6765-clk.h | 37 #define CLK_TOP_SYSPLL1_D2 2 macro
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| H A D | mt8173-clk.h | 54 #define CLK_TOP_SYSPLL1_D2 44 macro
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| H A D | mediatek,mt6795-clk.h | 52 #define CLK_TOP_SYSPLL1_D2 41 macro
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| H A D | mt2701-clk.h | 16 #define CLK_TOP_SYSPLL1_D2 6 macro
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| H A D | mt2712-clk.h | 37 #define CLK_TOP_SYSPLL1_D2 6 macro
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| H A D | mediatek,mt8365-clk.h | 17 #define CLK_TOP_SYSPLL1_D2 7 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt6795-topckgen.c | 406 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
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| H A D | clk-mt8173-topckgen.c | 485 FACTOR_FLAGS(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "main_h546m", 1, 2, 0),
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| H A D | clk-mt7622.c | 273 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
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| H A D | clk-mt7629.c | 378 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
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| H A D | clk-mt2712.c | 45 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
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| H A D | clk-mt8365.c | 36 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
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| H A D | clk-mt6797.c | 27 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
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