1274955Ssvnmir/* SPDX-License-Identifier: GPL-2.0 */ 2274955Ssvnmir 3353358Sdim#ifndef _DT_BINDINGS_CLK_MT6765_H 4353358Sdim#define _DT_BINDINGS_CLK_MT6765_H 5353358Sdim 6274955Ssvnmir/* FIX Clks */ 7274955Ssvnmir#define CLK_TOP_CLK26M 0 8274955Ssvnmir 9274955Ssvnmir/* APMIXEDSYS */ 10274955Ssvnmir#define CLK_APMIXED_ARMPLL_L 0 11274955Ssvnmir#define CLK_APMIXED_ARMPLL 1 12274955Ssvnmir#define CLK_APMIXED_CCIPLL 2 13274955Ssvnmir#define CLK_APMIXED_MAINPLL 3 14274955Ssvnmir#define CLK_APMIXED_MFGPLL 4 15274955Ssvnmir#define CLK_APMIXED_MMPLL 5 16274955Ssvnmir#define CLK_APMIXED_UNIV2PLL 6 17274955Ssvnmir#define CLK_APMIXED_MSDCPLL 7 18280031Sdim#define CLK_APMIXED_APLL1 8 19280031Sdim#define CLK_APMIXED_MPLL 9 20274955Ssvnmir#define CLK_APMIXED_ULPOSC1 10 21274955Ssvnmir#define CLK_APMIXED_ULPOSC2 11 22274955Ssvnmir#define CLK_APMIXED_SSUSB26M 12 23274955Ssvnmir#define CLK_APMIXED_APPLL26M 13 24274955Ssvnmir#define CLK_APMIXED_MIPIC0_26M 14 25274955Ssvnmir#define CLK_APMIXED_MDPLLGP26M 15 26274955Ssvnmir#define CLK_APMIXED_MMSYS_F26M 16 27274955Ssvnmir#define CLK_APMIXED_UFS26M 17 28274955Ssvnmir#define CLK_APMIXED_MIPIC1_26M 18 29274955Ssvnmir#define CLK_APMIXED_MEMPLL26M 19 30274955Ssvnmir#define CLK_APMIXED_CLKSQ_LVPLL_26M 20 31274955Ssvnmir#define CLK_APMIXED_MIPID0_26M 21 32274955Ssvnmir#define CLK_APMIXED_NR_CLK 22 33274955Ssvnmir 34274955Ssvnmir/* TOPCKGEN */ 35274955Ssvnmir#define CLK_TOP_SYSPLL 0 36274955Ssvnmir#define CLK_TOP_SYSPLL_D2 1 37274955Ssvnmir#define CLK_TOP_SYSPLL1_D2 2 38274955Ssvnmir#define CLK_TOP_SYSPLL1_D4 3 39274955Ssvnmir#define CLK_TOP_SYSPLL1_D8 4 40274955Ssvnmir#define CLK_TOP_SYSPLL1_D16 5 41274955Ssvnmir#define CLK_TOP_SYSPLL_D3 6 42274955Ssvnmir#define CLK_TOP_SYSPLL2_D2 7 43274955Ssvnmir#define CLK_TOP_SYSPLL2_D4 8 44274955Ssvnmir#define CLK_TOP_SYSPLL2_D8 9 45274955Ssvnmir#define CLK_TOP_SYSPLL_D5 10 46274955Ssvnmir#define CLK_TOP_SYSPLL3_D2 11 47274955Ssvnmir#define CLK_TOP_SYSPLL3_D4 12 48274955Ssvnmir#define CLK_TOP_SYSPLL_D7 13 49274955Ssvnmir#define CLK_TOP_SYSPLL4_D2 14 50274955Ssvnmir#define CLK_TOP_SYSPLL4_D4 15 51274955Ssvnmir#define CLK_TOP_USB20_192M 16 52274955Ssvnmir#define CLK_TOP_USB20_192M_D4 17 53274955Ssvnmir#define CLK_TOP_USB20_192M_D8 18 54274955Ssvnmir#define CLK_TOP_USB20_192M_D16 19 55274955Ssvnmir#define CLK_TOP_USB20_192M_D32 20 56274955Ssvnmir#define CLK_TOP_UNIVPLL 21 57274955Ssvnmir#define CLK_TOP_UNIVPLL_D2 22 58274955Ssvnmir#define CLK_TOP_UNIVPLL1_D2 23 59274955Ssvnmir#define CLK_TOP_UNIVPLL1_D4 24 60274955Ssvnmir#define CLK_TOP_UNIVPLL_D3 25 61274955Ssvnmir#define CLK_TOP_UNIVPLL2_D2 26 62274955Ssvnmir#define CLK_TOP_UNIVPLL2_D4 27 63274955Ssvnmir#define CLK_TOP_UNIVPLL2_D8 28 64274955Ssvnmir#define CLK_TOP_UNIVPLL2_D32 29 65274955Ssvnmir#define CLK_TOP_UNIVPLL_D5 30 66274955Ssvnmir#define CLK_TOP_UNIVPLL3_D2 31 67274955Ssvnmir#define CLK_TOP_UNIVPLL3_D4 32 68274955Ssvnmir#define CLK_TOP_MMPLL 33 69309124Sdim#define CLK_TOP_MMPLL_D2 34 70353358Sdim#define CLK_TOP_MPLL 35 71274955Ssvnmir#define CLK_TOP_DA_MPLL_104M_DIV 36 72274955Ssvnmir#define CLK_TOP_DA_MPLL_52M_DIV 37 73274955Ssvnmir#define CLK_TOP_MFGPLL 38 74274955Ssvnmir#define CLK_TOP_MSDCPLL 39 75274955Ssvnmir#define CLK_TOP_MSDCPLL_D2 40 76274955Ssvnmir#define CLK_TOP_APLL1 41 77274955Ssvnmir#define CLK_TOP_APLL1_D2 42 78274955Ssvnmir#define CLK_TOP_APLL1_D4 43 79274955Ssvnmir#define CLK_TOP_APLL1_D8 44 80274955Ssvnmir#define CLK_TOP_ULPOSC1 45 81274955Ssvnmir#define CLK_TOP_ULPOSC1_D2 46 82274955Ssvnmir#define CLK_TOP_ULPOSC1_D4 47 83274955Ssvnmir#define CLK_TOP_ULPOSC1_D8 48 84274955Ssvnmir#define CLK_TOP_ULPOSC1_D16 49 85274955Ssvnmir#define CLK_TOP_ULPOSC1_D32 50 86274955Ssvnmir#define CLK_TOP_DMPLL 51 87274955Ssvnmir#define CLK_TOP_F_FRTC 52 88274955Ssvnmir#define CLK_TOP_F_F26M 53 89274955Ssvnmir#define CLK_TOP_AXI 54 90274955Ssvnmir#define CLK_TOP_MM 55 91274955Ssvnmir#define CLK_TOP_SCP 56 92274955Ssvnmir#define CLK_TOP_MFG 57 93274955Ssvnmir#define CLK_TOP_F_FUART 58 94274955Ssvnmir#define CLK_TOP_SPI 59 95274955Ssvnmir#define CLK_TOP_MSDC50_0 60 96274955Ssvnmir#define CLK_TOP_MSDC30_1 61 97274955Ssvnmir#define CLK_TOP_AUDIO 62 98274955Ssvnmir#define CLK_TOP_AUD_1 63 99274955Ssvnmir#define CLK_TOP_AUD_ENGEN1 64 100274955Ssvnmir#define CLK_TOP_F_FDISP_PWM 65 101274955Ssvnmir#define CLK_TOP_SSPM 66 102274955Ssvnmir#define CLK_TOP_DXCC 67 103274955Ssvnmir#define CLK_TOP_I2C 68 104288943Sdim#define CLK_TOP_F_FPWM 69 105288943Sdim#define CLK_TOP_F_FSENINF 70 106274955Ssvnmir#define CLK_TOP_AES_FDE 71 107274955Ssvnmir#define CLK_TOP_F_BIST2FPC 72 108274955Ssvnmir#define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 109274955Ssvnmir#define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 110309124Sdim#define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 111314564Sdim#define CLK_TOP_DA_USB20_48M_DIV 76 112309124Sdim#define CLK_TOP_DA_UNIV_48M_DIV 77 113309124Sdim#define CLK_TOP_APLL12_DIV0 78 114353358Sdim#define CLK_TOP_APLL12_DIV1 79 115274955Ssvnmir#define CLK_TOP_APLL12_DIV2 80 116274955Ssvnmir#define CLK_TOP_APLL12_DIV3 81 117274955Ssvnmir#define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 118274955Ssvnmir#define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 119274955Ssvnmir#define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 120274955Ssvnmir#define CLK_TOP_FMEM_OCC_DRC_EN 85 121274955Ssvnmir#define CLK_TOP_USB20_48M_EN 86 122274955Ssvnmir#define CLK_TOP_UNIVPLL_48M_EN 87 123274955Ssvnmir#define CLK_TOP_MPLL_104M_EN 88 124274955Ssvnmir#define CLK_TOP_MPLL_52M_EN 89 125274955Ssvnmir#define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 126274955Ssvnmir#define CLK_TOP_F_BIST2FPC_EN 91 127274955Ssvnmir#define CLK_TOP_MD_32K 92 128274955Ssvnmir#define CLK_TOP_MD_26M 93 129274955Ssvnmir#define CLK_TOP_MD2_32K 94 130274955Ssvnmir#define CLK_TOP_MD2_26M 95 131274955Ssvnmir#define CLK_TOP_AXI_SEL 96 132274955Ssvnmir#define CLK_TOP_MEM_SEL 97 133274955Ssvnmir#define CLK_TOP_MM_SEL 98 134309124Sdim#define CLK_TOP_SCP_SEL 99 135274955Ssvnmir#define CLK_TOP_MFG_SEL 100 136274955Ssvnmir#define CLK_TOP_ATB_SEL 101 137274955Ssvnmir#define CLK_TOP_CAMTG_SEL 102 138274955Ssvnmir#define CLK_TOP_CAMTG1_SEL 103 139274955Ssvnmir#define CLK_TOP_CAMTG2_SEL 104 140274955Ssvnmir#define CLK_TOP_CAMTG3_SEL 105 141274955Ssvnmir#define CLK_TOP_UART_SEL 106 142274955Ssvnmir#define CLK_TOP_SPI_SEL 107 143274955Ssvnmir#define CLK_TOP_MSDC50_0_HCLK_SEL 108 144274955Ssvnmir#define CLK_TOP_MSDC50_0_SEL 109 145274955Ssvnmir#define CLK_TOP_MSDC30_1_SEL 110 146274955Ssvnmir#define CLK_TOP_AUDIO_SEL 111 147274955Ssvnmir#define CLK_TOP_AUD_INTBUS_SEL 112 148274955Ssvnmir#define CLK_TOP_AUD_1_SEL 113 149274955Ssvnmir#define CLK_TOP_AUD_ENGEN1_SEL 114 150274955Ssvnmir#define CLK_TOP_DISP_PWM_SEL 115 151274955Ssvnmir#define CLK_TOP_SSPM_SEL 116 152274955Ssvnmir#define CLK_TOP_DXCC_SEL 117 153274955Ssvnmir#define CLK_TOP_USB_TOP_SEL 118 154288943Sdim#define CLK_TOP_SPM_SEL 119 155274955Ssvnmir#define CLK_TOP_I2C_SEL 120 156353358Sdim#define CLK_TOP_PWM_SEL 121 157353358Sdim#define CLK_TOP_SENINF_SEL 122 158353358Sdim#define CLK_TOP_AES_FDE_SEL 123 159353358Sdim#define CLK_TOP_PWRAP_ULPOSC_SEL 124 160280031Sdim#define CLK_TOP_CAMTM_SEL 125 161280031Sdim#define CLK_TOP_NR_CLK 126 162280031Sdim 163280031Sdim/* INFRACFG */ 164280031Sdim#define CLK_IFR_ICUSB 0 165280031Sdim#define CLK_IFR_GCE 1 166274955Ssvnmir#define CLK_IFR_THERM 2 167274955Ssvnmir#define CLK_IFR_I2C_AP 3 168274955Ssvnmir#define CLK_IFR_I2C_CCU 4 169274955Ssvnmir#define CLK_IFR_I2C_SSPM 5 170274955Ssvnmir#define CLK_IFR_I2C_RSV 6 171274955Ssvnmir#define CLK_IFR_PWM_HCLK 7 172274955Ssvnmir#define CLK_IFR_PWM1 8 173274955Ssvnmir#define CLK_IFR_PWM2 9 174274955Ssvnmir#define CLK_IFR_PWM3 10 175274955Ssvnmir#define CLK_IFR_PWM4 11 176274955Ssvnmir#define CLK_IFR_PWM5 12 177274955Ssvnmir#define CLK_IFR_PWM 13 178274955Ssvnmir#define CLK_IFR_UART0 14 179274955Ssvnmir#define CLK_IFR_UART1 15 180274955Ssvnmir#define CLK_IFR_GCE_26M 16 181274955Ssvnmir#define CLK_IFR_CQ_DMA_FPC 17 182274955Ssvnmir#define CLK_IFR_BTIF 18 183274955Ssvnmir#define CLK_IFR_SPI0 19 184321369Sdim#define CLK_IFR_MSDC0 20 185321369Sdim#define CLK_IFR_MSDC1 21 186321369Sdim#define CLK_IFR_TRNG 22 187321369Sdim#define CLK_IFR_AUXADC 23 188321369Sdim#define CLK_IFR_CCIF1_AP 24 189321369Sdim#define CLK_IFR_CCIF1_MD 25 190321369Sdim#define CLK_IFR_AUXADC_MD 26 191321369Sdim#define CLK_IFR_AP_DMA 27 192321369Sdim#define CLK_IFR_DEVICE_APC 28 193321369Sdim#define CLK_IFR_CCIF_AP 29 194274955Ssvnmir#define CLK_IFR_AUDIO 30 195280031Sdim#define CLK_IFR_CCIF_MD 31 196280031Sdim#define CLK_IFR_RG_PWM_FBCLK6 32 197274955Ssvnmir#define CLK_IFR_DISP_PWM 33 198274955Ssvnmir#define CLK_IFR_CLDMA_BCLK 34 199274955Ssvnmir#define CLK_IFR_AUDIO_26M_BCLK 35 200321369Sdim#define CLK_IFR_SPI1 36 201274955Ssvnmir#define CLK_IFR_I2C4 37 202321369Sdim#define CLK_IFR_SPI2 38 203274955Ssvnmir#define CLK_IFR_SPI3 39 204274955Ssvnmir#define CLK_IFR_I2C5 40 205274955Ssvnmir#define CLK_IFR_I2C5_ARBITER 41 206274955Ssvnmir#define CLK_IFR_I2C5_IMM 42 207274955Ssvnmir#define CLK_IFR_I2C1_ARBITER 43 208274955Ssvnmir#define CLK_IFR_I2C1_IMM 44 209274955Ssvnmir#define CLK_IFR_I2C2_ARBITER 45 210274955Ssvnmir#define CLK_IFR_I2C2_IMM 46 211274955Ssvnmir#define CLK_IFR_SPI4 47 212274955Ssvnmir#define CLK_IFR_SPI5 48 213274955Ssvnmir#define CLK_IFR_CQ_DMA 49 214274955Ssvnmir#define CLK_IFR_FAES_FDE 50 215274955Ssvnmir#define CLK_IFR_MSDC0_SELF 51 216274955Ssvnmir#define CLK_IFR_MSDC1_SELF 52 217274955Ssvnmir#define CLK_IFR_I2C6 53 218274955Ssvnmir#define CLK_IFR_AP_MSDC0 54 219274955Ssvnmir#define CLK_IFR_MD_MSDC0 55 220274955Ssvnmir#define CLK_IFR_MSDC0_SRC 56 221336970Semaste#define CLK_IFR_MSDC1_SRC 57 222336970Semaste#define CLK_IFR_AES_TOP0_BCLK 58 223274955Ssvnmir#define CLK_IFR_MCU_PM_BCLK 59 224274955Ssvnmir#define CLK_IFR_CCIF2_AP 60 225274955Ssvnmir#define CLK_IFR_CCIF2_MD 61 226274955Ssvnmir#define CLK_IFR_CCIF3_AP 62 227280031Sdim#define CLK_IFR_CCIF3_MD 63 228280031Sdim#define CLK_IFR_NR_CLK 64 229321369Sdim 230280031Sdim/* AUDIO */ 231274955Ssvnmir#define CLK_AUDIO_AFE 0 232274955Ssvnmir#define CLK_AUDIO_22M 1 233274955Ssvnmir#define CLK_AUDIO_APLL_TUNER 2 234274955Ssvnmir#define CLK_AUDIO_ADC 3 235274955Ssvnmir#define CLK_AUDIO_DAC 4 236274955Ssvnmir#define CLK_AUDIO_DAC_PREDIS 5 237274955Ssvnmir#define CLK_AUDIO_TML 6 238274955Ssvnmir#define CLK_AUDIO_I2S1_BCLK 7 239274955Ssvnmir#define CLK_AUDIO_I2S2_BCLK 8 240274955Ssvnmir#define CLK_AUDIO_I2S3_BCLK 9 241274955Ssvnmir#define CLK_AUDIO_I2S4_BCLK 10 242274955Ssvnmir#define CLK_AUDIO_NR_CLK 11 243274955Ssvnmir 244274955Ssvnmir/* MIPI_RX_ANA_CSI0A */ 245274955Ssvnmir 246274955Ssvnmir#define CLK_MIPI0A_CSR_CSI_EN_0A 0 247274955Ssvnmir#define CLK_MIPI0A_NR_CLK 1 248274955Ssvnmir 249274955Ssvnmir/* MMSYS_CONFIG */ 250274955Ssvnmir 251274955Ssvnmir#define CLK_MM_MDP_RDMA0 0 252274955Ssvnmir#define CLK_MM_MDP_CCORR0 1 253280031Sdim#define CLK_MM_MDP_RSZ0 2 254#define CLK_MM_MDP_RSZ1 3 255#define CLK_MM_MDP_TDSHP0 4 256#define CLK_MM_MDP_WROT0 5 257#define CLK_MM_MDP_WDMA0 6 258#define CLK_MM_DISP_OVL0 7 259#define CLK_MM_DISP_OVL0_2L 8 260#define CLK_MM_DISP_RSZ0 9 261#define CLK_MM_DISP_RDMA0 10 262#define CLK_MM_DISP_WDMA0 11 263#define CLK_MM_DISP_COLOR0 12 264#define CLK_MM_DISP_CCORR0 13 265#define CLK_MM_DISP_AAL0 14 266#define CLK_MM_DISP_GAMMA0 15 267#define CLK_MM_DISP_DITHER0 16 268#define CLK_MM_DSI0 17 269#define CLK_MM_FAKE_ENG 18 270#define CLK_MM_SMI_COMMON 19 271#define CLK_MM_SMI_LARB0 20 272#define CLK_MM_SMI_COMM0 21 273#define CLK_MM_SMI_COMM1 22 274#define CLK_MM_CAM_MDP 23 275#define CLK_MM_SMI_IMG 24 276#define CLK_MM_SMI_CAM 25 277#define CLK_MM_IMG_DL_RELAY 26 278#define CLK_MM_IMG_DL_ASYNC_TOP 27 279#define CLK_MM_DIG_DSI 28 280#define CLK_MM_F26M_HRTWT 29 281#define CLK_MM_NR_CLK 30 282 283/* IMGSYS */ 284 285#define CLK_IMG_LARB2 0 286#define CLK_IMG_DIP 1 287#define CLK_IMG_FDVT 2 288#define CLK_IMG_DPE 3 289#define CLK_IMG_RSC 4 290#define CLK_IMG_NR_CLK 5 291 292/* VENCSYS */ 293 294#define CLK_VENC_SET0_LARB 0 295#define CLK_VENC_SET1_VENC 1 296#define CLK_VENC_SET2_JPGENC 2 297#define CLK_VENC_SET3_VDEC 3 298#define CLK_VENC_NR_CLK 4 299 300/* CAMSYS */ 301 302#define CLK_CAM_LARB3 0 303#define CLK_CAM_DFP_VAD 1 304#define CLK_CAM 2 305#define CLK_CAMTG 3 306#define CLK_CAM_SENINF 4 307#define CLK_CAMSV0 5 308#define CLK_CAMSV1 6 309#define CLK_CAMSV2 7 310#define CLK_CAM_CCU 8 311#define CLK_CAM_NR_CLK 9 312 313#endif /* _DT_BINDINGS_CLK_MT6765_H */ 314