1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2017 MediaTek Inc. 4 * Author: Weiyi Lu <weiyi.lu@mediatek.com> 5 */ 6 7#include <linux/clk.h> 8#include <linux/delay.h> 9#include <linux/mfd/syscon.h> 10#include <linux/mod_devicetable.h> 11#include <linux/platform_device.h> 12#include <linux/slab.h> 13 14#include "clk-gate.h" 15#include "clk-mtk.h" 16 17#include <dt-bindings/clock/mt2712-clk.h> 18 19static DEFINE_SPINLOCK(mt2712_clk_lock); 20 21static const struct mtk_fixed_clk top_fixed_clks[] = { 22 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000), 23 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000), 24 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000), 25 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000), 26 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000), 27 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000), 28 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000), 29 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000), 30 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768), 31 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747), 32 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000), 33 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000), 34}; 35 36static const struct mtk_fixed_factor top_divs[] = { 37 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1, 1), 38 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1, 2), 39 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1, 1), 40 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1, 2), 41 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1, 3), 42 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1, 1), 43 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1), 44 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1, 2), 45 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2), 46 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4), 47 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8), 48 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16), 49 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1, 3), 50 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2), 51 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4), 52 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1, 5), 53 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2), 54 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4), 55 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1, 7), 56 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2), 57 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4), 58 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1), 59 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1, 7), 60 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1, 26), 61 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1, 52), 62 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1, 104), 63 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1, 208), 64 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1, 2), 65 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2), 66 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4), 67 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8), 68 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1, 3), 69 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2), 70 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4), 71 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8), 72 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1, 5), 73 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2), 74 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4), 75 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8), 76 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1, 1), 77 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1, 1), 78 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1, 1), 79 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1, 1), 80 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1, 1), 81 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1, 1), 82 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1), 83 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2), 84 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4), 85 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8), 86 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1, 16), 87 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1), 88 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2), 89 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1, 4), 90 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1, 8), 91 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1, 16), 92 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1, 1), 93 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1, 2), 94 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1, 4), 95 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1, 8), 96 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1, 1), 97 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1, 2), 98 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1, 4), 99 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1, 8), 100 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1, 1), 101 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1, 1), 102 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1, 1), 103 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1, 2), 104 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1), 105 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2), 106 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1, 1), 107 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1, 2), 108 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1, 1), 109 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1, 2), 110 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1), 111 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2), 112 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1, 4), 113 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1, 8), 114 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1, 1), 115 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1, 2), 116 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1, 4), 117 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1), 118 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2), 119 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1, 4), 120 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1, 1), 121 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1, 2), 122 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1, 4), 123 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1, 4), 124 FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1, 3), 125 FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1, 3), 126}; 127 128static const char * const axi_parents[] = { 129 "clk26m", 130 "syspll1_d2", 131 "syspll_d5", 132 "syspll1_d4", 133 "univpll_d5", 134 "univpll2_d2", 135 "msdcpll2_ck" 136}; 137 138static const char * const mem_parents[] = { 139 "clk26m", 140 "dmpll_ck" 141}; 142 143static const char * const mm_parents[] = { 144 "clk26m", 145 "vencpll_ck", 146 "syspll_d3", 147 "syspll1_d2", 148 "syspll_d5", 149 "syspll1_d4", 150 "univpll1_d2", 151 "univpll2_d2" 152}; 153 154static const char * const pwm_parents[] = { 155 "clk26m", 156 "univpll2_d4", 157 "univpll3_d2", 158 "univpll1_d4" 159}; 160 161static const char * const vdec_parents[] = { 162 "clk26m", 163 "vcodecpll_ck", 164 "tvdpll_429m", 165 "univpll_d3", 166 "vencpll_ck", 167 "syspll_d3", 168 "univpll1_d2", 169 "mmpll_d2", 170 "syspll3_d2", 171 "tvdpll_ck" 172}; 173 174static const char * const venc_parents[] = { 175 "clk26m", 176 "univpll1_d2", 177 "mmpll_d2", 178 "tvdpll_d2", 179 "syspll1_d2", 180 "univpll_d5", 181 "vcodecpll_d2", 182 "univpll2_d2", 183 "syspll3_d2" 184}; 185 186static const char * const mfg_parents[] = { 187 "clk26m", 188 "mmpll_ck", 189 "univpll_d3", 190 "clk26m", 191 "clk26m", 192 "clk26m", 193 "clk26m", 194 "clk26m", 195 "clk26m", 196 "syspll_d3", 197 "syspll1_d2", 198 "syspll_d5", 199 "univpll_d3", 200 "univpll1_d2", 201 "univpll_d5", 202 "univpll2_d2" 203}; 204 205static const char * const camtg_parents[] = { 206 "clk26m", 207 "univpll_d52", 208 "univpll_d208", 209 "univpll_d104", 210 "clk26m_d2", 211 "univpll_d26", 212 "univpll2_d8", 213 "syspll3_d4", 214 "syspll3_d2", 215 "univpll1_d4", 216 "univpll2_d2" 217}; 218 219static const char * const uart_parents[] = { 220 "clk26m", 221 "univpll2_d8" 222}; 223 224static const char * const spi_parents[] = { 225 "clk26m", 226 "univpll2_d4", 227 "univpll1_d4", 228 "univpll2_d2", 229 "univpll3_d2", 230 "univpll1_d8" 231}; 232 233static const char * const usb20_parents[] = { 234 "clk26m", 235 "univpll1_d8", 236 "univpll3_d4" 237}; 238 239static const char * const usb30_parents[] = { 240 "clk26m", 241 "univpll3_d2", 242 "univpll3_d4", 243 "univpll2_d4" 244}; 245 246static const char * const msdc50_0_h_parents[] = { 247 "clk26m", 248 "syspll1_d2", 249 "syspll2_d2", 250 "syspll4_d2", 251 "univpll_d5", 252 "univpll1_d4" 253}; 254 255static const char * const msdc50_0_parents[] = { 256 "clk26m", 257 "msdcpll_ck", 258 "msdcpll_d2", 259 "univpll1_d4", 260 "syspll2_d2", 261 "msdcpll_d4", 262 "vencpll_d2", 263 "univpll1_d2", 264 "msdcpll2_ck", 265 "msdcpll2_d2", 266 "msdcpll2_d4" 267}; 268 269static const char * const msdc30_1_parents[] = { 270 "clk26m", 271 "univpll2_d2", 272 "msdcpll_d2", 273 "univpll1_d4", 274 "syspll2_d2", 275 "univpll_d7", 276 "vencpll_d2" 277}; 278 279static const char * const msdc30_3_parents[] = { 280 "clk26m", 281 "msdcpll2_ck", 282 "msdcpll2_d2", 283 "univpll2_d2", 284 "msdcpll2_d4", 285 "univpll1_d4", 286 "syspll2_d2", 287 "syspll_d7", 288 "univpll_d7", 289 "vencpll_d2", 290 "msdcpll_ck", 291 "msdcpll_d2", 292 "msdcpll_d4" 293}; 294 295static const char * const audio_parents[] = { 296 "clk26m", 297 "syspll3_d4", 298 "syspll4_d4", 299 "syspll1_d16" 300}; 301 302static const char * const aud_intbus_parents[] = { 303 "clk26m", 304 "syspll1_d4", 305 "syspll4_d2", 306 "univpll3_d2", 307 "univpll2_d8", 308 "syspll3_d2", 309 "syspll3_d4" 310}; 311 312static const char * const pmicspi_parents[] = { 313 "clk26m", 314 "syspll1_d8", 315 "syspll3_d4", 316 "syspll1_d16", 317 "univpll3_d4", 318 "univpll_d26", 319 "syspll3_d4" 320}; 321 322static const char * const dpilvds1_parents[] = { 323 "clk26m", 324 "lvdspll2_ck", 325 "lvdspll2_d2", 326 "lvdspll2_d4", 327 "lvdspll2_d8", 328 "clkfpc" 329}; 330 331static const char * const atb_parents[] = { 332 "clk26m", 333 "syspll1_d2", 334 "univpll_d5", 335 "syspll_d5" 336}; 337 338static const char * const nr_parents[] = { 339 "clk26m", 340 "univpll1_d4", 341 "syspll2_d2", 342 "syspll1_d4", 343 "univpll1_d8", 344 "univpll3_d2", 345 "univpll2_d2", 346 "syspll_d5" 347}; 348 349static const char * const nfi2x_parents[] = { 350 "clk26m", 351 "syspll4_d4", 352 "univpll3_d4", 353 "univpll1_d8", 354 "syspll2_d4", 355 "univpll3_d2", 356 "syspll_d7", 357 "syspll2_d2", 358 "univpll2_d2", 359 "syspll_d5", 360 "syspll1_d2" 361}; 362 363static const char * const irda_parents[] = { 364 "clk26m", 365 "univpll2_d4", 366 "syspll2_d4", 367 "univpll2_d8" 368}; 369 370static const char * const cci400_parents[] = { 371 "clk26m", 372 "vencpll_ck", 373 "armca35pll_600m", 374 "armca35pll_400m", 375 "univpll_d2", 376 "syspll_d2", 377 "msdcpll_ck", 378 "univpll_d3" 379}; 380 381static const char * const aud_1_parents[] = { 382 "clk26m", 383 "apll1_ck", 384 "univpll2_d4", 385 "univpll2_d8" 386}; 387 388static const char * const aud_2_parents[] = { 389 "clk26m", 390 "apll2_ck", 391 "univpll2_d4", 392 "univpll2_d8" 393}; 394 395static const char * const mem_mfg_parents[] = { 396 "clk26m", 397 "mmpll_ck", 398 "univpll_d3" 399}; 400 401static const char * const axi_mfg_parents[] = { 402 "clk26m", 403 "axi_sel", 404 "univpll_d5" 405}; 406 407static const char * const scam_parents[] = { 408 "clk26m", 409 "syspll3_d2", 410 "univpll2_d4", 411 "syspll2_d4" 412}; 413 414static const char * const nfiecc_parents[] = { 415 "clk26m", 416 "nfi2x_sel", 417 "syspll_d7", 418 "syspll2_d2", 419 "univpll2_d2", 420 "univpll_d5", 421 "syspll1_d2" 422}; 423 424static const char * const pe2_mac_p0_parents[] = { 425 "clk26m", 426 "syspll1_d8", 427 "syspll4_d2", 428 "syspll2_d4", 429 "univpll2_d4", 430 "syspll3_d2" 431}; 432 433static const char * const dpilvds_parents[] = { 434 "clk26m", 435 "lvdspll_ck", 436 "lvdspll_d2", 437 "lvdspll_d4", 438 "lvdspll_d8", 439 "clkfpc" 440}; 441 442static const char * const hdcp_parents[] = { 443 "clk26m", 444 "syspll4_d2", 445 "syspll3_d4", 446 "univpll2_d4" 447}; 448 449static const char * const hdcp_24m_parents[] = { 450 "clk26m", 451 "univpll_d26", 452 "univpll_d52", 453 "univpll2_d8" 454}; 455 456static const char * const rtc_parents[] = { 457 "clkrtc_int", 458 "clkrtc_ext", 459 "clk26m", 460 "univpll3_d8" 461}; 462 463static const char * const spinor_parents[] = { 464 "clk26m", 465 "clk26m_d2", 466 "syspll4_d4", 467 "univpll2_d8", 468 "univpll3_d4", 469 "syspll4_d2", 470 "syspll2_d4", 471 "univpll2_d4", 472 "etherpll_125m", 473 "syspll1_d4" 474}; 475 476static const char * const apll_parents[] = { 477 "clk26m", 478 "apll1_ck", 479 "apll1_d2", 480 "apll1_d4", 481 "apll1_d8", 482 "apll1_d16", 483 "apll2_ck", 484 "apll2_d2", 485 "apll2_d4", 486 "apll2_d8", 487 "apll2_d16", 488 "clk26m", 489 "clk26m" 490}; 491 492static const char * const a1sys_hp_parents[] = { 493 "clk26m", 494 "apll1_ck", 495 "apll1_d2", 496 "apll1_d4", 497 "apll1_d8", 498 "apll1_d3" 499}; 500 501static const char * const a2sys_hp_parents[] = { 502 "clk26m", 503 "apll2_ck", 504 "apll2_d2", 505 "apll2_d4", 506 "apll2_d8", 507 "apll2_d3" 508}; 509 510static const char * const asm_l_parents[] = { 511 "clk26m", 512 "univpll2_d4", 513 "univpll2_d2", 514 "syspll_d5" 515}; 516 517static const char * const i2so1_parents[] = { 518 "clk26m", 519 "apll1_ck", 520 "apll2_ck" 521}; 522 523static const char * const ether_125m_parents[] = { 524 "clk26m", 525 "etherpll_125m", 526 "univpll3_d2" 527}; 528 529static const char * const ether_50m_parents[] = { 530 "clk26m", 531 "etherpll_50m", 532 "apll1_d3", 533 "univpll3_d4" 534}; 535 536static const char * const jpgdec_parents[] = { 537 "clk26m", 538 "univpll_d3", 539 "tvdpll_429m", 540 "vencpll_ck", 541 "syspll_d3", 542 "vcodecpll_ck", 543 "univpll1_d2", 544 "armca35pll_400m", 545 "tvdpll_429m_d2", 546 "tvdpll_429m_d4" 547}; 548 549static const char * const spislv_parents[] = { 550 "clk26m", 551 "univpll2_d4", 552 "univpll1_d4", 553 "univpll2_d2", 554 "univpll3_d2", 555 "univpll1_d8", 556 "univpll1_d2", 557 "univpll_d5" 558}; 559 560static const char * const ether_parents[] = { 561 "clk26m", 562 "etherpll_50m", 563 "univpll_d26" 564}; 565 566static const char * const di_parents[] = { 567 "clk26m", 568 "tvdpll_d2", 569 "tvdpll_d4", 570 "tvdpll_d8", 571 "vencpll_ck", 572 "vencpll_d2", 573 "cvbs", 574 "cvbs_d2" 575}; 576 577static const char * const tvd_parents[] = { 578 "clk26m", 579 "cvbs_d2", 580 "univpll2_d8" 581}; 582 583static const char * const i2c_parents[] = { 584 "clk26m", 585 "univpll_d26", 586 "univpll2_d4", 587 "univpll3_d2", 588 "univpll1_d4" 589}; 590 591static const char * const msdc0p_aes_parents[] = { 592 "clk26m", 593 "syspll_d2", 594 "univpll_d3", 595 "vcodecpll_ck" 596}; 597 598static const char * const cmsys_parents[] = { 599 "clk26m", 600 "univpll_d3", 601 "syspll_d3", 602 "syspll1_d2", 603 "syspll2_d2" 604}; 605 606static const char * const gcpu_parents[] = { 607 "clk26m", 608 "syspll_d3", 609 "syspll1_d2", 610 "univpll1_d2", 611 "univpll_d5", 612 "univpll3_d2", 613 "univpll_d3" 614}; 615 616static const char * const aud_apll1_parents[] = { 617 "apll1", 618 "clkaud_ext_i_1" 619}; 620 621static const char * const aud_apll2_parents[] = { 622 "apll2", 623 "clkaud_ext_i_2" 624}; 625 626static const char * const apll1_ref_parents[] = { 627 "clkaud_ext_i_2", 628 "clkaud_ext_i_1", 629 "clki2si0_mck_i", 630 "clki2si1_mck_i", 631 "clki2si2_mck_i", 632 "clktdmin_mclk_i", 633 "clki2si2_mck_i", 634 "clktdmin_mclk_i" 635}; 636 637static const char * const audull_vtx_parents[] = { 638 "d2a_ulclk_6p5m", 639 "clkaud_ext_i_0" 640}; 641 642static struct mtk_composite top_muxes[] = { 643 /* CLK_CFG_0 */ 644 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3, 645 7, CLK_IS_CRITICAL), 646 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1, 647 15, CLK_IS_CRITICAL), 648 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 24, 3, 31), 649 /* CLK_CFG_1 */ 650 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x050, 0, 2, 7), 651 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x050, 8, 4, 15), 652 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x050, 16, 4, 23), 653 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x050, 24, 4, 31), 654 /* CLK_CFG_2 */ 655 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x060, 0, 4, 7), 656 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060, 8, 1, 15), 657 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x060, 16, 3, 23), 658 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x060, 24, 2, 31), 659 /* CLK_CFG_3 */ 660 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel", usb30_parents, 0x070, 0, 2, 7), 661 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel", msdc50_0_h_parents, 662 0x070, 8, 3, 15), 663 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 664 0x070, 16, 4, 23), 665 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 666 0x070, 24, 3, 31), 667 /* CLK_CFG_4 */ 668 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_1_parents, 669 0x080, 0, 3, 7), 670 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_3_parents, 671 0x080, 8, 4, 15), 672 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 673 0x080, 16, 2, 23), 674 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 675 0x080, 24, 3, 31), 676 /* CLK_CFG_5 */ 677 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x090, 0, 3, 7), 678 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel", dpilvds1_parents, 679 0x090, 8, 3, 15), 680 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x090, 16, 2, 23), 681 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_parents, 0x090, 24, 3, 31), 682 /* CLK_CFG_6 */ 683 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x0a0, 0, 4, 7), 684 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0a0, 8, 2, 15), 685 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x0a0, 16, 3, 23), 686 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x0a0, 24, 2, 31), 687 /* CLK_CFG_7 */ 688 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x0b0, 0, 2, 7), 689 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel", mem_mfg_parents, 690 0x0b0, 8, 2, 15), 691 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel", axi_mfg_parents, 692 0x0b0, 16, 2, 23), 693 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel", scam_parents, 0x0b0, 24, 2, 31), 694 /* CLK_CFG_8 */ 695 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents, 0x0c0, 0, 3, 7), 696 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel", pe2_mac_p0_parents, 697 0x0c0, 8, 3, 15), 698 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel", pe2_mac_p0_parents, 699 0x0c0, 16, 3, 23), 700 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x0c0, 24, 3, 31), 701 /* CLK_CFG_9 */ 702 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel", msdc50_0_h_parents, 703 0x0d0, 0, 3, 7), 704 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel", hdcp_parents, 0x0d0, 8, 2, 15), 705 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel", hdcp_24m_parents, 706 0x0d0, 16, 2, 23), 707 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 708 0x0d0, 24, 2, 31, CLK_IS_CRITICAL), 709 /* CLK_CFG_10 */ 710 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents, 0x500, 0, 4, 7), 711 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x500, 8, 4, 15), 712 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel", apll_parents, 0x500, 16, 4, 23), 713 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents, 714 0x500, 24, 3, 31), 715 /* CLK_CFG_11 */ 716 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a2sys_hp_parents, 0x510, 0, 3, 7), 717 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents, 0x510, 8, 2, 15), 718 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents, 0x510, 16, 2, 23), 719 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents, 0x510, 24, 2, 31), 720 /* CLK_CFG_12 */ 721 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel", i2so1_parents, 0x520, 0, 2, 7), 722 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel", i2so1_parents, 0x520, 8, 2, 15), 723 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel", i2so1_parents, 0x520, 16, 2, 23), 724 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel", i2so1_parents, 0x520, 24, 2, 31), 725 /* CLK_CFG_13 */ 726 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel", i2so1_parents, 0x530, 0, 2, 7), 727 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel", i2so1_parents, 0x530, 8, 2, 15), 728 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel", i2so1_parents, 0x530, 16, 2, 23), 729 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel", i2so1_parents, 0x530, 24, 2, 31), 730 /* CLK_CFG_14 */ 731 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel", ether_125m_parents, 732 0x540, 0, 2, 7), 733 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel", ether_50m_parents, 734 0x540, 8, 2, 15), 735 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel", jpgdec_parents, 0x540, 16, 4, 23), 736 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel", spislv_parents, 0x540, 24, 3, 31), 737 /* CLK_CFG_15 */ 738 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel", ether_parents, 0x550, 0, 2, 7), 739 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel", camtg_parents, 0x550, 8, 4, 15), 740 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x550, 16, 3, 23), 741 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel", tvd_parents, 0x550, 24, 2, 31), 742 /* CLK_CFG_16 */ 743 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x560, 0, 3, 7), 744 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel", pwm_parents, 0x560, 8, 2, 15), 745 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel", msdc0p_aes_parents, 746 0x560, 16, 2, 23), 747 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x560, 24, 3, 31), 748 /* CLK_CFG_17 */ 749 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x570, 0, 3, 7), 750 /* CLK_AUDDIV_4 */ 751 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel", aud_apll1_parents, 0x134, 0, 1), 752 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel", aud_apll2_parents, 0x134, 1, 1), 753 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel", audull_vtx_parents, 754 0x134, 31, 1), 755 MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel", apll1_ref_parents, 0x134, 4, 3), 756 MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel", apll1_ref_parents, 0x134, 7, 3), 757}; 758 759static const char * const mcu_mp0_parents[] = { 760 "clk26m", 761 "armca35pll_ck", 762 "f_mp0_pll1_ck", 763 "f_mp0_pll2_ck" 764}; 765 766static const char * const mcu_mp2_parents[] = { 767 "clk26m", 768 "armca72pll_ck", 769 "f_big_pll1_ck", 770 "f_big_pll2_ck" 771}; 772 773static const char * const mcu_bus_parents[] = { 774 "clk26m", 775 "cci400_sel", 776 "f_bus_pll1_ck", 777 "f_bus_pll2_ck" 778}; 779 780static struct mtk_composite mcu_muxes[] = { 781 /* mp0_pll_divider_cfg */ 782 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0, 783 9, 2, -1, CLK_IS_CRITICAL), 784 /* mp2_pll_divider_cfg */ 785 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8, 786 9, 2, -1, CLK_IS_CRITICAL), 787 /* bus_pll_divider_cfg */ 788 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 789 9, 2, -1, CLK_IS_CRITICAL), 790}; 791 792static const struct mtk_clk_divider top_adj_divs[] = { 793 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8), 794 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8), 795 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8), 796 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8), 797 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8), 798 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8), 799 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8), 800 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8), 801}; 802 803static const struct mtk_gate_regs top0_cg_regs = { 804 .set_ofs = 0x120, 805 .clr_ofs = 0x120, 806 .sta_ofs = 0x120, 807}; 808 809static const struct mtk_gate_regs top1_cg_regs = { 810 .set_ofs = 0x424, 811 .clr_ofs = 0x424, 812 .sta_ofs = 0x424, 813}; 814 815#define GATE_TOP0(_id, _name, _parent, _shift) \ 816 GATE_MTK(_id, _name, _parent, &top0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) 817 818#define GATE_TOP1(_id, _name, _parent, _shift) \ 819 GATE_MTK(_id, _name, _parent, &top1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 820 821static const struct mtk_gate top_clks[] = { 822 /* TOP0 */ 823 GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0), 824 GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1), 825 GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2), 826 GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3), 827 GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4), 828 GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5), 829 GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6), 830 GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7), 831 /* TOP1 */ 832 GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0), 833 GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1), 834 GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2), 835}; 836 837static const struct mtk_gate_regs infra_cg_regs = { 838 .set_ofs = 0x40, 839 .clr_ofs = 0x44, 840 .sta_ofs = 0x48, 841}; 842 843#define GATE_INFRA(_id, _name, _parent, _shift) \ 844 GATE_MTK(_id, _name, _parent, &infra_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 845 846static const struct mtk_gate infra_clks[] = { 847 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), 848 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6), 849 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8), 850 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16), 851 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24), 852 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25), 853 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26), 854}; 855 856static const struct mtk_gate_regs peri0_cg_regs = { 857 .set_ofs = 0x8, 858 .clr_ofs = 0x10, 859 .sta_ofs = 0x18, 860}; 861 862static const struct mtk_gate_regs peri1_cg_regs = { 863 .set_ofs = 0xc, 864 .clr_ofs = 0x14, 865 .sta_ofs = 0x1c, 866}; 867 868static const struct mtk_gate_regs peri2_cg_regs = { 869 .set_ofs = 0x42c, 870 .clr_ofs = 0x42c, 871 .sta_ofs = 0x42c, 872}; 873 874#define GATE_PERI0(_id, _name, _parent, _shift) \ 875 GATE_MTK(_id, _name, _parent, &peri0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 876 877#define GATE_PERI1(_id, _name, _parent, _shift) \ 878 GATE_MTK(_id, _name, _parent, &peri1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) 879 880#define GATE_PERI2(_id, _name, _parent, _shift) \ 881 GATE_MTK(_id, _name, _parent, &peri2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv) 882 883static const struct mtk_gate peri_clks[] = { 884 /* PERI0 */ 885 GATE_PERI0(CLK_PERI_NFI, "per_nfi", "axi_sel", 0), 886 GATE_PERI0(CLK_PERI_THERM, "per_therm", "axi_sel", 1), 887 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0", "pwm_sel", 2), 888 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1", "pwm_sel", 3), 889 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2", "pwm_sel", 4), 890 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3", "pwm_sel", 5), 891 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4", "pwm_sel", 6), 892 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5", "pwm_sel", 7), 893 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6", "pwm_sel", 8), 894 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7", "pwm_sel", 9), 895 GATE_PERI0(CLK_PERI_PWM, "per_pwm", "pwm_sel", 10), 896 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma", "axi_sel", 13), 897 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0", "msdc50_0_sel", 14), 898 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1", "msdc30_1_sel", 15), 899 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2", "msdc30_2_sel", 16), 900 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3", "msdc30_3_sel", 17), 901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20), 902 GATE_PERI0(CLK_PERI_UART1, "per_uart1", "uart_sel", 21), 903 GATE_PERI0(CLK_PERI_UART2, "per_uart2", "uart_sel", 22), 904 GATE_PERI0(CLK_PERI_UART3, "per_uart3", "uart_sel", 23), 905 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0", "axi_sel", 24), 906 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1", "axi_sel", 25), 907 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2", "axi_sel", 26), 908 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3", "axi_sel", 27), 909 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4", "axi_sel", 28), 910 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc", "ltepll_fs26m", 29), 911 GATE_PERI0(CLK_PERI_SPI0, "per_spi0", "spi_sel", 30), 912 /* PERI1 */ 913 GATE_PERI1(CLK_PERI_SPI, "per_spi", "spinor_sel", 1), 914 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5", "axi_sel", 3), 915 GATE_PERI1(CLK_PERI_SPI2, "per_spi2", "spi_sel", 5), 916 GATE_PERI1(CLK_PERI_SPI3, "per_spi3", "spi_sel", 6), 917 GATE_PERI1(CLK_PERI_SPI5, "per_spi5", "spi_sel", 8), 918 GATE_PERI1(CLK_PERI_UART4, "per_uart4", "uart_sel", 9), 919 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash", "uart_sel", 11), 920 GATE_PERI1(CLK_PERI_GMAC, "per_gmac", "uart_sel", 12), 921 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0", "uart_sel", 14), 922 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1", "uart_sel", 15), 923 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk", "uart_sel", 16), 924 /* PERI2 */ 925 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en", "msdc50_0_sel", 0), 926 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en", "msdc30_1_sel", 1), 927 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en", "msdc30_2_sel", 2), 928 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en", "msdc30_3_sel", 3), 929 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h", "msdc50_0_h_sel", 4), 930 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h", "msdc50_3_h_sel", 5), 931 GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q", "axi_sel", 6), 932 GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q", "mem_sel", 7), 933}; 934 935static u16 infrasys_rst_ofs[] = { 0x30, 0x34, }; 936static u16 pericfg_rst_ofs[] = { 0x0, 0x4, }; 937 938static const struct mtk_clk_rst_desc clk_rst_desc[] = { 939 /* infra */ 940 { 941 .version = MTK_RST_SIMPLE, 942 .rst_bank_ofs = infrasys_rst_ofs, 943 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs), 944 }, 945 /* peri */ 946 { 947 .version = MTK_RST_SIMPLE, 948 .rst_bank_ofs = pericfg_rst_ofs, 949 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs), 950 }, 951}; 952 953static const struct mtk_clk_desc topck_desc = { 954 .clks = top_clks, 955 .num_clks = ARRAY_SIZE(top_clks), 956 .fixed_clks = top_fixed_clks, 957 .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), 958 .factor_clks = top_divs, 959 .num_factor_clks = ARRAY_SIZE(top_divs), 960 .composite_clks = top_muxes, 961 .num_composite_clks = ARRAY_SIZE(top_muxes), 962 .divider_clks = top_adj_divs, 963 .num_divider_clks = ARRAY_SIZE(top_adj_divs), 964 .clk_lock = &mt2712_clk_lock, 965}; 966 967static const struct mtk_clk_desc mcu_desc = { 968 .composite_clks = mcu_muxes, 969 .num_composite_clks = ARRAY_SIZE(mcu_muxes), 970 .clk_lock = &mt2712_clk_lock, 971}; 972 973static const struct mtk_clk_desc infra_desc = { 974 .clks = infra_clks, 975 .num_clks = ARRAY_SIZE(infra_clks), 976 .rst_desc = &clk_rst_desc[0], 977}; 978 979static const struct mtk_clk_desc peri_desc = { 980 .clks = peri_clks, 981 .num_clks = ARRAY_SIZE(peri_clks), 982 .rst_desc = &clk_rst_desc[1], 983}; 984 985static const struct of_device_id of_match_clk_mt2712[] = { 986 { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, 987 { .compatible = "mediatek,mt2712-mcucfg", .data = &mcu_desc }, 988 { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, 989 { .compatible = "mediatek,mt2712-topckgen", .data = &topck_desc }, 990 { /* sentinel */ } 991}; 992MODULE_DEVICE_TABLE(of, of_match_clk_mt2712); 993 994static struct platform_driver clk_mt2712_drv = { 995 .probe = mtk_clk_simple_probe, 996 .remove_new = mtk_clk_simple_remove, 997 .driver = { 998 .name = "clk-mt2712", 999 .of_match_table = of_match_clk_mt2712, 1000 }, 1001}; 1002module_platform_driver(clk_mt2712_drv); 1003MODULE_LICENSE("GPL"); 1004