1250003Sadrian/* SPDX-License-Identifier: GPL-2.0-only */ 2250003Sadrian/* 3250003Sadrian * Copyright (c) 2017 MediaTek Inc. 4250003Sadrian * Author: Kevin Chen <kevin-cw.chen@mediatek.com> 5250003Sadrian */ 6250003Sadrian 7250003Sadrian#ifndef _DT_BINDINGS_CLK_MT6797_H 8250003Sadrian#define _DT_BINDINGS_CLK_MT6797_H 9250003Sadrian 10250003Sadrian/* TOPCKGEN */ 11250003Sadrian#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX_PRE 1 12250003Sadrian#define CLK_TOP_MUX_ULPOSC_AXI_CK_MUX 2 13250003Sadrian#define CLK_TOP_MUX_AXI 3 14250003Sadrian#define CLK_TOP_MUX_MEM 4 15250003Sadrian#define CLK_TOP_MUX_DDRPHYCFG 5 16250003Sadrian#define CLK_TOP_MUX_MM 6 17250003Sadrian#define CLK_TOP_MUX_PWM 7 18250003Sadrian#define CLK_TOP_MUX_VDEC 8 19250003Sadrian#define CLK_TOP_MUX_VENC 9 20250003Sadrian#define CLK_TOP_MUX_MFG 10 21250003Sadrian#define CLK_TOP_MUX_CAMTG 11 22250003Sadrian#define CLK_TOP_MUX_UART 12 23250003Sadrian#define CLK_TOP_MUX_SPI 13 24250003Sadrian#define CLK_TOP_MUX_ULPOSC_SPI_CK_MUX 14 25250003Sadrian#define CLK_TOP_MUX_USB20 15 26250003Sadrian#define CLK_TOP_MUX_MSDC50_0_HCLK 16 27250003Sadrian#define CLK_TOP_MUX_MSDC50_0 17 28250008Sadrian#define CLK_TOP_MUX_MSDC30_1 18 29250008Sadrian#define CLK_TOP_MUX_MSDC30_2 19 30250008Sadrian#define CLK_TOP_MUX_AUDIO 20 31250003Sadrian#define CLK_TOP_MUX_AUD_INTBUS 21 32250003Sadrian#define CLK_TOP_MUX_PMICSPI 22 33250003Sadrian#define CLK_TOP_MUX_SCP 23 34250003Sadrian#define CLK_TOP_MUX_ATB 24 35250003Sadrian#define CLK_TOP_MUX_MJC 25 36250003Sadrian#define CLK_TOP_MUX_DPI0 26 37250003Sadrian#define CLK_TOP_MUX_AUD_1 27 38250003Sadrian#define CLK_TOP_MUX_AUD_2 28 39250003Sadrian#define CLK_TOP_MUX_SSUSB_TOP_SYS 29 40250003Sadrian#define CLK_TOP_MUX_SPM 30 41250003Sadrian#define CLK_TOP_MUX_BSI_SPI 31 42250003Sadrian#define CLK_TOP_MUX_AUDIO_H 32 43250003Sadrian#define CLK_TOP_MUX_ANC_MD32 33 44250003Sadrian#define CLK_TOP_MUX_MFG_52M 34 45250003Sadrian#define CLK_TOP_SYSPLL_CK 35 46250008Sadrian#define CLK_TOP_SYSPLL_D2 36 47250003Sadrian#define CLK_TOP_SYSPLL1_D2 37 48250003Sadrian#define CLK_TOP_SYSPLL1_D4 38 49250003Sadrian#define CLK_TOP_SYSPLL1_D8 39 50250003Sadrian#define CLK_TOP_SYSPLL1_D16 40 51250003Sadrian#define CLK_TOP_SYSPLL_D3 41 52250003Sadrian#define CLK_TOP_SYSPLL_D3_D3 42 53250003Sadrian#define CLK_TOP_SYSPLL2_D2 43 54250003Sadrian#define CLK_TOP_SYSPLL2_D4 44 55250003Sadrian#define CLK_TOP_SYSPLL2_D8 45 56250003Sadrian#define CLK_TOP_SYSPLL_D5 46 57250003Sadrian#define CLK_TOP_SYSPLL3_D2 47 58250003Sadrian#define CLK_TOP_SYSPLL3_D4 48 59250003Sadrian#define CLK_TOP_SYSPLL_D7 49 60250003Sadrian#define CLK_TOP_SYSPLL4_D2 50 61250003Sadrian#define CLK_TOP_SYSPLL4_D4 51 62250003Sadrian#define CLK_TOP_UNIVPLL_CK 52 63250003Sadrian#define CLK_TOP_UNIVPLL_D7 53 64250003Sadrian#define CLK_TOP_UNIVPLL_D26 54 65250003Sadrian#define CLK_TOP_SSUSB_PHY_48M_CK 55 66250003Sadrian#define CLK_TOP_USB_PHY48M_CK 56 67250003Sadrian#define CLK_TOP_UNIVPLL_D2 57 68250003Sadrian#define CLK_TOP_UNIVPLL1_D2 58 69250003Sadrian#define CLK_TOP_UNIVPLL1_D4 59 70250003Sadrian#define CLK_TOP_UNIVPLL1_D8 60 71250003Sadrian#define CLK_TOP_UNIVPLL_D3 61 72250003Sadrian#define CLK_TOP_UNIVPLL2_D2 62 73250003Sadrian#define CLK_TOP_UNIVPLL2_D4 63 74250003Sadrian#define CLK_TOP_UNIVPLL2_D8 64 75250003Sadrian#define CLK_TOP_UNIVPLL_D5 65 76250003Sadrian#define CLK_TOP_UNIVPLL3_D2 66 77250003Sadrian#define CLK_TOP_UNIVPLL3_D4 67 78250008Sadrian#define CLK_TOP_UNIVPLL3_D8 68 79250003Sadrian#define CLK_TOP_ULPOSC_CK_ORG 69 80250003Sadrian#define CLK_TOP_ULPOSC_CK 70 81250003Sadrian#define CLK_TOP_ULPOSC_D2 71 82250003Sadrian#define CLK_TOP_ULPOSC_D3 72 83250003Sadrian#define CLK_TOP_ULPOSC_D4 73 84250003Sadrian#define CLK_TOP_ULPOSC_D8 74 85250003Sadrian#define CLK_TOP_ULPOSC_D10 75 86250003Sadrian#define CLK_TOP_APLL1_CK 76 87250003Sadrian#define CLK_TOP_APLL2_CK 77 88250003Sadrian#define CLK_TOP_MFGPLL_CK 78 89250008Sadrian#define CLK_TOP_MFGPLL_D2 79 90250003Sadrian#define CLK_TOP_IMGPLL_CK 80 91250003Sadrian#define CLK_TOP_IMGPLL_D2 81 92250003Sadrian#define CLK_TOP_IMGPLL_D4 82 93250003Sadrian#define CLK_TOP_CODECPLL_CK 83 94250003Sadrian#define CLK_TOP_CODECPLL_D2 84 95250003Sadrian#define CLK_TOP_VDECPLL_CK 85 96250003Sadrian#define CLK_TOP_TVDPLL_CK 86 97250003Sadrian#define CLK_TOP_TVDPLL_D2 87 98250003Sadrian#define CLK_TOP_TVDPLL_D4 88 99250003Sadrian#define CLK_TOP_TVDPLL_D8 89 100250003Sadrian#define CLK_TOP_TVDPLL_D16 90 101250003Sadrian#define CLK_TOP_MSDCPLL_CK 91 102250008Sadrian#define CLK_TOP_MSDCPLL_D2 92 103250003Sadrian#define CLK_TOP_MSDCPLL_D4 93 104250003Sadrian#define CLK_TOP_MSDCPLL_D8 94 105250003Sadrian#define CLK_TOP_NR 95 106250008Sadrian 107250003Sadrian/* APMIXED_SYS */ 108250003Sadrian#define CLK_APMIXED_MAINPLL 1 109250003Sadrian#define CLK_APMIXED_UNIVPLL 2 110250003Sadrian#define CLK_APMIXED_MFGPLL 3 111250003Sadrian#define CLK_APMIXED_MSDCPLL 4 112250003Sadrian#define CLK_APMIXED_IMGPLL 5 113250003Sadrian#define CLK_APMIXED_TVDPLL 6 114250003Sadrian#define CLK_APMIXED_CODECPLL 7 115250003Sadrian#define CLK_APMIXED_VDECPLL 8 116250003Sadrian#define CLK_APMIXED_APLL1 9 117250003Sadrian#define CLK_APMIXED_APLL2 10 118250003Sadrian#define CLK_APMIXED_NR 11 119250008Sadrian 120250003Sadrian/* INFRA_SYS */ 121250003Sadrian#define CLK_INFRA_PMIC_TMR 1 122250003Sadrian#define CLK_INFRA_PMIC_AP 2 123250008Sadrian#define CLK_INFRA_PMIC_MD 3 124250003Sadrian#define CLK_INFRA_PMIC_CONN 4 125250003Sadrian#define CLK_INFRA_SCP 5 126250003Sadrian#define CLK_INFRA_SEJ 6 127250003Sadrian#define CLK_INFRA_APXGPT 7 128250003Sadrian#define CLK_INFRA_SEJ_13M 8 129250003Sadrian#define CLK_INFRA_ICUSB 9 130250003Sadrian#define CLK_INFRA_GCE 10 131250003Sadrian#define CLK_INFRA_THERM 11 132250003Sadrian#define CLK_INFRA_I2C0 12 133250003Sadrian#define CLK_INFRA_I2C1 13 134250003Sadrian#define CLK_INFRA_I2C2 14 135250003Sadrian#define CLK_INFRA_I2C3 15 136250003Sadrian#define CLK_INFRA_PWM_HCLK 16 137250003Sadrian#define CLK_INFRA_PWM1 17 138250003Sadrian#define CLK_INFRA_PWM2 18 139250003Sadrian#define CLK_INFRA_PWM3 19 140250003Sadrian#define CLK_INFRA_PWM4 20 141250003Sadrian#define CLK_INFRA_PWM 21 142250003Sadrian#define CLK_INFRA_UART0 22 143250003Sadrian#define CLK_INFRA_UART1 23 144250003Sadrian#define CLK_INFRA_UART2 24 145250003Sadrian#define CLK_INFRA_UART3 25 146250003Sadrian#define CLK_INFRA_MD2MD_CCIF_0 26 147250003Sadrian#define CLK_INFRA_MD2MD_CCIF_1 27 148250003Sadrian#define CLK_INFRA_MD2MD_CCIF_2 28 149250008Sadrian#define CLK_INFRA_FHCTL 29 150250003Sadrian#define CLK_INFRA_BTIF 30 151250003Sadrian#define CLK_INFRA_MD2MD_CCIF_3 31 152250003Sadrian#define CLK_INFRA_SPI 32 153250008Sadrian#define CLK_INFRA_MSDC0 33 154250003Sadrian#define CLK_INFRA_MD2MD_CCIF_4 34 155250003Sadrian#define CLK_INFRA_MSDC1 35 156250008Sadrian#define CLK_INFRA_MSDC2 36 157250003Sadrian#define CLK_INFRA_MD2MD_CCIF_5 37 158250003Sadrian#define CLK_INFRA_GCPU 38 159250008Sadrian#define CLK_INFRA_TRNG 39 160250003Sadrian#define CLK_INFRA_AUXADC 40 161250003Sadrian#define CLK_INFRA_CPUM 41 162250003Sadrian#define CLK_INFRA_AP_C2K_CCIF_0 42 163250003Sadrian#define CLK_INFRA_AP_C2K_CCIF_1 43 164250003Sadrian#define CLK_INFRA_CLDMA 44 165250003Sadrian#define CLK_INFRA_DISP_PWM 45 166250003Sadrian#define CLK_INFRA_AP_DMA 46 167250008Sadrian#define CLK_INFRA_DEVICE_APC 47 168250003Sadrian#define CLK_INFRA_L2C_SRAM 48 169250003Sadrian#define CLK_INFRA_CCIF_AP 49 170250003Sadrian#define CLK_INFRA_AUDIO 50 171250003Sadrian#define CLK_INFRA_CCIF_MD 51 172250003Sadrian#define CLK_INFRA_DRAMC_F26M 52 173250003Sadrian#define CLK_INFRA_I2C4 53 174250008Sadrian#define CLK_INFRA_I2C_APPM 54 175250003Sadrian#define CLK_INFRA_I2C_GPUPM 55 176250003Sadrian#define CLK_INFRA_I2C2_IMM 56 177250003Sadrian#define CLK_INFRA_I2C2_ARB 57 178250003Sadrian#define CLK_INFRA_I2C3_IMM 58 179250003Sadrian#define CLK_INFRA_I2C3_ARB 59 180250003Sadrian#define CLK_INFRA_I2C5 60 181250003Sadrian#define CLK_INFRA_SYS_CIRQ 61 182250003Sadrian#define CLK_INFRA_SPI1 62 183250003Sadrian#define CLK_INFRA_DRAMC_B_F26M 63 184250003Sadrian#define CLK_INFRA_ANC_MD32 64 185250003Sadrian#define CLK_INFRA_ANC_MD32_32K 65 186250003Sadrian#define CLK_INFRA_DVFS_SPM1 66 187250003Sadrian#define CLK_INFRA_AES_TOP0 67 188250003Sadrian#define CLK_INFRA_AES_TOP1 68 189250003Sadrian#define CLK_INFRA_SSUSB_BUS 69 190250003Sadrian#define CLK_INFRA_SPI2 70 191250003Sadrian#define CLK_INFRA_SPI3 71 192250003Sadrian#define CLK_INFRA_SPI4 72 193250003Sadrian#define CLK_INFRA_SPI5 73 194250003Sadrian#define CLK_INFRA_IRTX 74 195250003Sadrian#define CLK_INFRA_SSUSB_SYS 75 196250003Sadrian#define CLK_INFRA_SSUSB_REF 76 197250003Sadrian#define CLK_INFRA_AUDIO_26M 77 198250003Sadrian#define CLK_INFRA_AUDIO_26M_PAD_TOP 78 199250003Sadrian#define CLK_INFRA_MODEM_TEMP_SHARE 79 200250008Sadrian#define CLK_INFRA_VAD_WRAP_SOC 80 201250008Sadrian#define CLK_INFRA_DRAMC_CONF 81 202250008Sadrian#define CLK_INFRA_DRAMC_B_CONF 82 203250008Sadrian#define CLK_INFRA_MFG_VCG 83 204250003Sadrian#define CLK_INFRA_13M 84 205250003Sadrian#define CLK_INFRA_NR 85 206250003Sadrian 207250003Sadrian/* IMG_SYS */ 208250003Sadrian#define CLK_IMG_FDVT 1 209250008Sadrian#define CLK_IMG_DPE 2 210250003Sadrian#define CLK_IMG_DIP 3 211250008Sadrian#define CLK_IMG_LARB6 4 212250003Sadrian#define CLK_IMG_NR 5 213250003Sadrian 214250003Sadrian/* MM_SYS */ 215250003Sadrian#define CLK_MM_SMI_COMMON 1 216250003Sadrian#define CLK_MM_SMI_LARB0 2 217250003Sadrian#define CLK_MM_SMI_LARB5 3 218250003Sadrian#define CLK_MM_CAM_MDP 4 219250003Sadrian#define CLK_MM_MDP_RDMA0 5 220250003Sadrian#define CLK_MM_MDP_RDMA1 6 221250003Sadrian#define CLK_MM_MDP_RSZ0 7 222250003Sadrian#define CLK_MM_MDP_RSZ1 8 223250003Sadrian#define CLK_MM_MDP_RSZ2 9 224250003Sadrian#define CLK_MM_MDP_TDSHP 10 225250003Sadrian#define CLK_MM_MDP_COLOR 11 226250003Sadrian#define CLK_MM_MDP_WDMA 12 227250003Sadrian#define CLK_MM_MDP_WROT0 13 228250003Sadrian#define CLK_MM_MDP_WROT1 14 229250003Sadrian#define CLK_MM_FAKE_ENG 15 230250003Sadrian#define CLK_MM_DISP_OVL0 16 231250003Sadrian#define CLK_MM_DISP_OVL1 17 232250003Sadrian#define CLK_MM_DISP_OVL0_2L 18 233250003Sadrian#define CLK_MM_DISP_OVL1_2L 19 234250003Sadrian#define CLK_MM_DISP_RDMA0 20 235250003Sadrian#define CLK_MM_DISP_RDMA1 21 236250003Sadrian#define CLK_MM_DISP_WDMA0 22 237250003Sadrian#define CLK_MM_DISP_WDMA1 23 238250003Sadrian#define CLK_MM_DISP_COLOR 24 239250003Sadrian#define CLK_MM_DISP_CCORR 25 240250003Sadrian#define CLK_MM_DISP_AAL 26 241250003Sadrian#define CLK_MM_DISP_GAMMA 27 242250003Sadrian#define CLK_MM_DISP_OD 28 243250003Sadrian#define CLK_MM_DISP_DITHER 29 244250003Sadrian#define CLK_MM_DISP_UFOE 30 245250003Sadrian#define CLK_MM_DISP_DSC 31 246250003Sadrian#define CLK_MM_DISP_SPLIT 32 247250003Sadrian#define CLK_MM_DSI0_MM_CLOCK 33 248250003Sadrian#define CLK_MM_DSI1_MM_CLOCK 34 249250003Sadrian#define CLK_MM_DPI_MM_CLOCK 35 250250003Sadrian#define CLK_MM_DPI_INTERFACE_CLOCK 36 251250003Sadrian#define CLK_MM_LARB4_AXI_ASIF_MM_CLOCK 37 252250003Sadrian#define CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK 38 253250003Sadrian#define CLK_MM_DISP_OVL0_MOUT_CLOCK 39 254250008Sadrian#define CLK_MM_FAKE_ENG2 40 255250003Sadrian#define CLK_MM_DSI0_INTERFACE_CLOCK 41 256250003Sadrian#define CLK_MM_DSI1_INTERFACE_CLOCK 42 257250003Sadrian#define CLK_MM_NR 43 258250003Sadrian 259250003Sadrian/* VDEC_SYS */ 260250003Sadrian#define CLK_VDEC_CKEN_ENG 1 261250003Sadrian#define CLK_VDEC_ACTIVE 2 262250003Sadrian#define CLK_VDEC_CKEN 3 263250003Sadrian#define CLK_VDEC_LARB1_CKEN 4 264250003Sadrian#define CLK_VDEC_NR 5 265250003Sadrian 266250003Sadrian/* VENC_SYS */ 267250003Sadrian#define CLK_VENC_0 1 268250003Sadrian#define CLK_VENC_1 2 269250003Sadrian#define CLK_VENC_2 3 270250003Sadrian#define CLK_VENC_3 4 271250003Sadrian#define CLK_VENC_NR 5 272250003Sadrian 273250003Sadrian#endif /* _DT_BINDINGS_CLK_MT6797_H */ 274250003Sadrian