| /linux-master/sound/soc/mediatek/mt8186/ |
| H A D | mt8186-afe-clk.h | 73 CLK_TOP_APLL12_DIV1, enumerator in enum:__anon5164
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| H A D | mt8186-afe-clk.c | 66 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
524 .div_clk_id = CLK_TOP_APLL12_DIV1,
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| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 152 #define CLK_TOP_APLL12_DIV1 120 macro
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| H A D | mt6765-clk.h | 114 #define CLK_TOP_APLL12_DIV1 79 macro
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| H A D | mt6779-clk.h | 139 #define CLK_TOP_APLL12_DIV1 129 macro
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| H A D | mt8183-clk.h | 159 #define CLK_TOP_APLL12_DIV1 123 macro
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| H A D | mt8192-clk.h | 155 #define CLK_TOP_APLL12_DIV1 143 macro
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| H A D | mt8195-clk.h | 231 #define CLK_TOP_APLL12_DIV1 219 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 152 #define CLK_TOP_APLL12_DIV1 120 macro
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| H A D | mt6765-clk.h | 114 #define CLK_TOP_APLL12_DIV1 79 macro
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| H A D | mt6779-clk.h | 139 #define CLK_TOP_APLL12_DIV1 129 macro
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| H A D | mt8183-clk.h | 159 #define CLK_TOP_APLL12_DIV1 123 macro
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| H A D | mt8192-clk.h | 155 #define CLK_TOP_APLL12_DIV1 143 macro
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| H A D | mt8195-clk.h | 231 #define CLK_TOP_APLL12_DIV1 219 macro
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| /linux-master/sound/soc/mediatek/mt8183/ |
| H A D | mt8183-afe-clk.c | 45 CLK_TOP_APLL12_DIV1, enumerator in enum:__anon406
84 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
518 .div_clk_id = CLK_TOP_APLL12_DIV1,
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| /linux-master/sound/soc/mediatek/mt8192/ |
| H A D | mt8192-afe-clk.h | 207 CLK_TOP_APLL12_DIV1, enumerator in enum:__anon408
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| H A D | mt8192-afe-clk.c | 50 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
435 .div_clk_id = CLK_TOP_APLL12_DIV1,
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8167.c | 851 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
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| H A D | clk-mt8516.c | 633 GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
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| H A D | clk-mt6765.c | 517 GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
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| H A D | clk-mt8183.c | 626 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel", 0x320, 3, 0x324, 8, 8),
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| H A D | clk-mt8192.c | 701 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8),
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| H A D | clk-mt6779.c | 829 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
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| H A D | clk-mt8195-topckgen.c | 1178 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "top_i2si2_mck", 0x0320, 1, 0x0328, 8, 8),
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