1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * mt8192-afe-clk.h -- Mediatek 8192 afe clock ctrl definition 4 * 5 * Copyright (c) 2020 MediaTek Inc. 6 * Author: Shane Chien <shane.chien@mediatek.com> 7 */ 8 9#ifndef _MT8192_AFE_CLOCK_CTRL_H_ 10#define _MT8192_AFE_CLOCK_CTRL_H_ 11 12#define AP_PLL_CON3 0x0014 13#define APLL1_CON0 0x0318 14#define APLL1_CON1 0x031c 15#define APLL1_CON2 0x0320 16#define APLL1_CON4 0x0328 17#define APLL1_TUNER_CON0 0x0040 18 19#define APLL2_CON0 0x032c 20#define APLL2_CON1 0x0330 21#define APLL2_CON2 0x0334 22#define APLL2_CON4 0x033c 23#define APLL2_TUNER_CON0 0x0044 24 25#define CLK_CFG_7 0x0080 26#define CLK_CFG_8 0x0090 27#define CLK_CFG_11 0x00c0 28#define CLK_CFG_12 0x00d0 29#define CLK_CFG_13 0x00e0 30#define CLK_CFG_15 0x0100 31 32#define CLK_AUDDIV_0 0x0320 33#define CLK_AUDDIV_2 0x0328 34#define CLK_AUDDIV_3 0x0334 35#define CLK_AUDDIV_4 0x0338 36#define CKSYS_AUD_TOP_CFG 0x032c 37#define CKSYS_AUD_TOP_MON 0x0330 38 39#define PERI_BUS_DCM_CTRL 0x0074 40#define MODULE_SW_CG_1_STA 0x0094 41#define MODULE_SW_CG_2_STA 0x00ac 42 43/* CLK_AUDDIV_0 */ 44#define APLL12_DIV0_PDN_SFT 0 45#define APLL12_DIV0_PDN_MASK 0x1 46#define APLL12_DIV0_PDN_MASK_SFT (0x1 << 0) 47#define APLL12_DIV1_PDN_SFT 1 48#define APLL12_DIV1_PDN_MASK 0x1 49#define APLL12_DIV1_PDN_MASK_SFT (0x1 << 1) 50#define APLL12_DIV2_PDN_SFT 2 51#define APLL12_DIV2_PDN_MASK 0x1 52#define APLL12_DIV2_PDN_MASK_SFT (0x1 << 2) 53#define APLL12_DIV3_PDN_SFT 3 54#define APLL12_DIV3_PDN_MASK 0x1 55#define APLL12_DIV3_PDN_MASK_SFT (0x1 << 3) 56#define APLL12_DIV4_PDN_SFT 4 57#define APLL12_DIV4_PDN_MASK 0x1 58#define APLL12_DIV4_PDN_MASK_SFT (0x1 << 4) 59#define APLL12_DIVB_PDN_SFT 5 60#define APLL12_DIVB_PDN_MASK 0x1 61#define APLL12_DIVB_PDN_MASK_SFT (0x1 << 5) 62#define APLL12_DIV5_PDN_SFT 6 63#define APLL12_DIV5_PDN_MASK 0x1 64#define APLL12_DIV5_PDN_MASK_SFT (0x1 << 6) 65#define APLL12_DIV6_PDN_SFT 7 66#define APLL12_DIV6_PDN_MASK 0x1 67#define APLL12_DIV6_PDN_MASK_SFT (0x1 << 7) 68#define APLL12_DIV7_PDN_SFT 8 69#define APLL12_DIV7_PDN_MASK 0x1 70#define APLL12_DIV7_PDN_MASK_SFT (0x1 << 8) 71#define APLL12_DIV8_PDN_SFT 9 72#define APLL12_DIV8_PDN_MASK 0x1 73#define APLL12_DIV8_PDN_MASK_SFT (0x1 << 9) 74#define APLL12_DIV9_PDN_SFT 10 75#define APLL12_DIV9_PDN_MASK 0x1 76#define APLL12_DIV9_PDN_MASK_SFT (0x1 << 10) 77#define APLL_I2S0_MCK_SEL_SFT 16 78#define APLL_I2S0_MCK_SEL_MASK 0x1 79#define APLL_I2S0_MCK_SEL_MASK_SFT (0x1 << 16) 80#define APLL_I2S1_MCK_SEL_SFT 17 81#define APLL_I2S1_MCK_SEL_MASK 0x1 82#define APLL_I2S1_MCK_SEL_MASK_SFT (0x1 << 17) 83#define APLL_I2S2_MCK_SEL_SFT 18 84#define APLL_I2S2_MCK_SEL_MASK 0x1 85#define APLL_I2S2_MCK_SEL_MASK_SFT (0x1 << 18) 86#define APLL_I2S3_MCK_SEL_SFT 19 87#define APLL_I2S3_MCK_SEL_MASK 0x1 88#define APLL_I2S3_MCK_SEL_MASK_SFT (0x1 << 19) 89#define APLL_I2S4_MCK_SEL_SFT 20 90#define APLL_I2S4_MCK_SEL_MASK 0x1 91#define APLL_I2S4_MCK_SEL_MASK_SFT (0x1 << 20) 92#define APLL_I2S5_MCK_SEL_SFT 21 93#define APLL_I2S5_MCK_SEL_MASK 0x1 94#define APLL_I2S5_MCK_SEL_MASK_SFT (0x1 << 21) 95#define APLL_I2S6_MCK_SEL_SFT 22 96#define APLL_I2S6_MCK_SEL_MASK 0x1 97#define APLL_I2S6_MCK_SEL_MASK_SFT (0x1 << 22) 98#define APLL_I2S7_MCK_SEL_SFT 23 99#define APLL_I2S7_MCK_SEL_MASK 0x1 100#define APLL_I2S7_MCK_SEL_MASK_SFT (0x1 << 23) 101#define APLL_I2S8_MCK_SEL_SFT 24 102#define APLL_I2S8_MCK_SEL_MASK 0x1 103#define APLL_I2S8_MCK_SEL_MASK_SFT (0x1 << 24) 104#define APLL_I2S9_MCK_SEL_SFT 25 105#define APLL_I2S9_MCK_SEL_MASK 0x1 106#define APLL_I2S9_MCK_SEL_MASK_SFT (0x1 << 25) 107 108/* CLK_AUDDIV_2 */ 109#define APLL12_CK_DIV0_SFT 0 110#define APLL12_CK_DIV0_MASK 0xff 111#define APLL12_CK_DIV0_MASK_SFT (0xff << 0) 112#define APLL12_CK_DIV1_SFT 8 113#define APLL12_CK_DIV1_MASK 0xff 114#define APLL12_CK_DIV1_MASK_SFT (0xff << 8) 115#define APLL12_CK_DIV2_SFT 16 116#define APLL12_CK_DIV2_MASK 0xff 117#define APLL12_CK_DIV2_MASK_SFT (0xff << 16) 118#define APLL12_CK_DIV3_SFT 24 119#define APLL12_CK_DIV3_MASK 0xff 120#define APLL12_CK_DIV3_MASK_SFT (0xff << 24) 121 122/* CLK_AUDDIV_3 */ 123#define APLL12_CK_DIV4_SFT 0 124#define APLL12_CK_DIV4_MASK 0xff 125#define APLL12_CK_DIV4_MASK_SFT (0xff << 0) 126#define APLL12_CK_DIVB_SFT 8 127#define APLL12_CK_DIVB_MASK 0xff 128#define APLL12_CK_DIVB_MASK_SFT (0xff << 8) 129#define APLL12_CK_DIV5_SFT 16 130#define APLL12_CK_DIV5_MASK 0xff 131#define APLL12_CK_DIV5_MASK_SFT (0xff << 16) 132#define APLL12_CK_DIV6_SFT 24 133#define APLL12_CK_DIV6_MASK 0xff 134#define APLL12_CK_DIV6_MASK_SFT (0xff << 24) 135 136/* CLK_AUDDIV_4 */ 137#define APLL12_CK_DIV7_SFT 0 138#define APLL12_CK_DIV7_MASK 0xff 139#define APLL12_CK_DIV7_MASK_SFT (0xff << 0) 140#define APLL12_CK_DIV8_SFT 8 141#define APLL12_CK_DIV8_MASK 0xff 142#define APLL12_CK_DIV8_MASK_SFT (0xff << 0) 143#define APLL12_CK_DIV9_SFT 16 144#define APLL12_CK_DIV9_MASK 0xff 145#define APLL12_CK_DIV9_MASK_SFT (0xff << 0) 146 147/* AUD_TOP_CFG */ 148#define AUD_TOP_CFG_SFT 0 149#define AUD_TOP_CFG_MASK 0xffffffff 150#define AUD_TOP_CFG_MASK_SFT (0xffffffff << 0) 151 152/* AUD_TOP_MON */ 153#define AUD_TOP_MON_SFT 0 154#define AUD_TOP_MON_MASK 0xffffffff 155#define AUD_TOP_MON_MASK_SFT (0xffffffff << 0) 156 157/* CLK_AUDDIV_3 */ 158#define APLL12_CK_DIV5_MSB_SFT 0 159#define APLL12_CK_DIV5_MSB_MASK 0xf 160#define APLL12_CK_DIV5_MSB_MASK_SFT (0xf << 0) 161#define RESERVED0_SFT 4 162#define RESERVED0_MASK 0xfffffff 163#define RESERVED0_MASK_SFT (0xfffffff << 4) 164 165/* APLL */ 166#define APLL1_W_NAME "APLL1" 167#define APLL2_W_NAME "APLL2" 168enum { 169 MT8192_APLL1 = 0, 170 MT8192_APLL2, 171}; 172 173enum { 174 CLK_AFE = 0, 175 CLK_TML, 176 CLK_APLL22M, 177 CLK_APLL24M, 178 CLK_APLL1_TUNER, 179 CLK_APLL2_TUNER, 180 CLK_NLE, 181 CLK_INFRA_SYS_AUDIO, 182 CLK_INFRA_AUDIO_26M, 183 CLK_MUX_AUDIO, 184 CLK_MUX_AUDIOINTBUS, 185 CLK_TOP_MAINPLL_D4_D4, 186 /* apll related mux */ 187 CLK_TOP_MUX_AUD_1, 188 CLK_TOP_APLL1_CK, 189 CLK_TOP_MUX_AUD_2, 190 CLK_TOP_APLL2_CK, 191 CLK_TOP_MUX_AUD_ENG1, 192 CLK_TOP_APLL1_D4, 193 CLK_TOP_MUX_AUD_ENG2, 194 CLK_TOP_APLL2_D4, 195 CLK_TOP_MUX_AUDIO_H, 196 CLK_TOP_I2S0_M_SEL, 197 CLK_TOP_I2S1_M_SEL, 198 CLK_TOP_I2S2_M_SEL, 199 CLK_TOP_I2S3_M_SEL, 200 CLK_TOP_I2S4_M_SEL, 201 CLK_TOP_I2S5_M_SEL, 202 CLK_TOP_I2S6_M_SEL, 203 CLK_TOP_I2S7_M_SEL, 204 CLK_TOP_I2S8_M_SEL, 205 CLK_TOP_I2S9_M_SEL, 206 CLK_TOP_APLL12_DIV0, 207 CLK_TOP_APLL12_DIV1, 208 CLK_TOP_APLL12_DIV2, 209 CLK_TOP_APLL12_DIV3, 210 CLK_TOP_APLL12_DIV4, 211 CLK_TOP_APLL12_DIVB, 212 CLK_TOP_APLL12_DIV5, 213 CLK_TOP_APLL12_DIV6, 214 CLK_TOP_APLL12_DIV7, 215 CLK_TOP_APLL12_DIV8, 216 CLK_TOP_APLL12_DIV9, 217 CLK_CLK26M, 218 CLK_NUM 219}; 220 221struct mtk_base_afe; 222 223int mt8192_init_clock(struct mtk_base_afe *afe); 224int mt8192_afe_enable_clock(struct mtk_base_afe *afe); 225void mt8192_afe_disable_clock(struct mtk_base_afe *afe); 226 227int mt8192_apll1_enable(struct mtk_base_afe *afe); 228void mt8192_apll1_disable(struct mtk_base_afe *afe); 229 230int mt8192_apll2_enable(struct mtk_base_afe *afe); 231void mt8192_apll2_disable(struct mtk_base_afe *afe); 232 233int mt8192_get_apll_rate(struct mtk_base_afe *afe, int apll); 234int mt8192_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 235int mt8192_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 236 237/* these will be replaced by using CCF */ 238int mt8192_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate); 239void mt8192_mck_disable(struct mtk_base_afe *afe, int mck_id); 240 241int mt8192_set_audio_int_bus_parent(struct mtk_base_afe *afe, 242 int clk_id); 243 244#endif 245