Searched refs:CLK_APMIXED_MAINPLL (Results 1 - 25 of 52) sorted by relevance

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/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt8135-clk.h110 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmt7629-clk.h156 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt8516-clk.h14 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt7622-clk.h171 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt6797-clk.h108 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt6765-clk.h13 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmt8173-clk.h158 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmediatek,mt6795-clk.h142 #define CLK_APMIXED_MAINPLL 1 macro
/linux-master/include/dt-bindings/clock/
H A Dmt8135-clk.h110 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmt7629-clk.h156 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt8516-clk.h14 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt7622-clk.h171 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt6797-clk.h108 #define CLK_APMIXED_MAINPLL 1 macro
H A Dmt6765-clk.h13 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmt8173-clk.h158 #define CLK_APMIXED_MAINPLL 3 macro
H A Dmediatek,mt6795-clk.h142 #define CLK_APMIXED_MAINPLL 1 macro
/linux-master/drivers/clk/mediatek/
H A Dclk-mt8516-apmixedsys.c62 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
H A Dclk-mt8192-apmixedsys.c73 PLL_B(CLK_APMIXED_MAINPLL, "mainpll", 0x0340, 0x034c, 0xff000000,
140 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
H A Dclk-mt8186-apmixedsys.c57 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
125 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
H A Dclk-mt6795-apmixedsys.c49 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR,
104 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
H A Dclk-mt8195-apmixedsys.c76 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
158 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
H A Dclk-mt8173-apmixedsys.c65 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21,
123 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x60),
H A Dclk-mt8167-apmixedsys.c61 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
H A Dclk-mt8188-apmixedsys.c71 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x045C, 0x0468, 0xff000000,
H A Dclk-mt8135-apmixedsys.c40 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),

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