Searched refs:NV_REG32 (Results 1 - 13 of 13) sorted by relevance
/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_i2c.c | 37 NV_REG32(NV32_FUNCSEL) &= ~0x00000010; 38 NV_REG32(NV32_2FUNCSEL) |= 0x00000010; 41 NV_REG32(NV32_2FUNCSEL) &= ~0x00000010; 42 NV_REG32(NV32_FUNCSEL) |= 0x00000010; 55 data32 = NV_REG32(NV32_NV4E_I2CBUS_0) & ~0x2f; 57 NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x21; 59 NV_REG32(NV32_NV4E_I2CBUS_0) = data32 | 0x01; 62 data32 = NV_REG32(NV32_NV4E_I2CBUS_1) & ~0x2f; 64 NV_REG32(NV32_NV4E_I2CBUS_1) = data32 | 0x21; 66 NV_REG32(NV32_NV4E_I2CBUS_ [all...] |
H A D | nv_agp.c | 32 LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); 36 reg = (NV_REG32(NV32_NVSTRAPINFO2) & ~0x00000800); 38 NV_REG32(NV32_NVSTRAPINFO2) = (reg | 0x80000000); 40 LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2)));
|
H A D | nv_info.c | 326 fb_mrs2 = NV_REG32(NV32_FB_MRS2); 327 fb_mrs1 = NV_REG32(NV32_FB_MRS1); 396 NV_REG32(NV32_FB_MRS2) = fb_mrs2; 397 NV_REG32(NV32_FB_MRS1) = fb_mrs1; 463 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 485 if (exec) NV_REG32(reg) = data2; 524 NV_REG32(reg) = data; 525 NV_REG32(reg) = data2; 569 data = NV_REG32(NV32_NV4STRAPINFO); 609 data = NV_REG32(re [all...] |
H A D | nv_acc_dma.c | 48 while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET) != (si->engine.dma.put << 2)) && 83 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; 85 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; 104 NV_REG32(cnt) = 0x00000000; 134 NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; 211 NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0; 647 NV_REG32(NVACC_NV10_TIL0AD + (cnt << 2)) = 648 NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2)); 679 tmp = (NV_REG32(NV32_NV4X_WHAT0) & 0x000000ff); 714 NV_REG32(NV32_NV44_WHAT1 [all...] |
H A D | nv_acc.c | 88 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; 90 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; 108 NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; 196 NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0; 472 NV_REG32(NV32_NV44_WHAT10) = NV_REG32(NV32_NV10STRAPINFO); 473 NV_REG32(NV32_NV44_WHAT11) = 0x00000000; 474 NV_REG32(NV32_NV44_WHAT12) = 0x00000000; 475 NV_REG32(NV32_NV44_WHAT13) = NV_REG32(NV32_NV10STRAPINF [all...] |
H A D | nv_crtc.c | 657 NV_REG32(NV32_LVDS_PWR) = 0x00000003; 700 NV_REG32(NV32_LVDS_PWR) = 0x00000007; 770 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 806 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 846 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); 859 NV_REG32(NV32_CURCONF) = 0x02000100; 988 while ((((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) && 1000 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 1098 NV_REG32(NV32_2FUNCSEL) &= ~0x00000100; 1099 NV_REG32(NV32_FUNCSE [all...] |
H A D | nv_crtc2.c | 639 NV_REG32(NV32_LVDS_PWR) = 0x00000003; 681 NV_REG32(NV32_LVDS_PWR) = 0x00000007; 750 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 767 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 806 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 819 NV_REG32(NV32_2CURCONF) = 0x02000100; 1008 NV_REG32(NV32_FUNCSEL) &= ~0x00000100; 1009 NV_REG32(NV32_2FUNCSEL) |= 0x00000100;
|
H A D | nv_bes.c | 360 NV_REG32(NV32_FUNCSEL) &= ~0x00001000; 361 NV_REG32(NV32_2FUNCSEL) |= 0x00001000; 368 NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; 369 NV_REG32(NV32_FUNCSEL) |= 0x00001000;
|
H A D | nv_dac2.c | 187 LOG(4,("DAC2: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040)));
|
H A D | nv_general.c | 1722 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; 1747 NV_REG32(NV32_PWRUPCTRL) = 0xffff00ff; 1749 NV_REG32(NV32_PWRUPCTRL) = 0xffffffff; 1771 NV_REG32(NV32_2FUNCSEL) &= ~0x00001100; 1772 NV_REG32(NV32_FUNCSEL) |= 0x00001100; 1875 NV_REG32(NV32_PFB_CLS_PAGE2) &= 0xffff7fff;
|
H A D | nv_dac.c | 222 LOG(4,("DAC: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040)));
|
/haiku/src/add-ons/kernel/drivers/graphics/nvidia/ |
H A D | driver.c | 426 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 434 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 442 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 444 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 446 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 454 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 456 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 464 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 472 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 480 NV_REG32(NV32_CRTC2_INT [all...] |
/haiku/headers/private/graphics/nvidia/ |
H A D | nv_macros.h | 890 #define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] macro 903 #define DACR(A) (NV_REG32(NVDAC_##A)) 904 #define DACW(A,B) (NV_REG32(NVDAC_##A)=B) 907 #define DAC2R(A) (NV_REG32(NVDAC2_##A)) 908 #define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) 911 #define BESR(A) (NV_REG32(NVBES_##A)) 912 #define BESW(A,B) (NV_REG32(NVBES_##A)=B) 939 #define ACCR(A) (NV_REG32(NVACC_##A)) 940 #define ACCW(A,B) (NV_REG32(NVACC_##A)=B)
|
Completed in 181 milliseconds