1/* 2 Copyright 1999, Be Incorporated. All Rights Reserved. 3 This file may be used under the terms of the Be Sample Code License. 4 5 Other authors: 6 Mark Watson; 7 Rudolf Cornelissen 3/2002-11/2022. 8*/ 9 10 11#include "AGP.h" 12#include "DriverInterface.h" 13#include "nv_macros.h" 14 15#include <graphic_driver.h> 16#include <KernelExport.h> 17#include <SupportDefs.h> 18#include <ISA.h> 19#include <PCI.h> 20#include <OS.h> 21#include <directories.h> 22#include <driver_settings.h> 23 24#include <stdlib.h> 25#include <stdio.h> 26#include <string.h> 27 28#define TRACE(x...) dprintf("nvidia: " x) 29#define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 30 31#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) 32#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) 33 34#define MAX_DEVICES 8 35 36/* Tell the kernel what revision of the driver API we support */ 37int32 api_version = B_CUR_DRIVER_API_VERSION; 38 39/* these structures are private to the kernel driver */ 40typedef struct device_info device_info; 41 42typedef struct { 43 timer te; /* timer entry for add_timer() */ 44 device_info *di; /* pointer to the owning device */ 45 bigtime_t when_target; /* when we're supposed to wake up */ 46} timer_info; 47 48struct device_info { 49 uint32 is_open; /* a count of how many times the devices has been opened */ 50 area_id shared_area; /* the area shared between the driver and all of the accelerants */ 51 shared_info *si; /* a pointer to the shared area, for convenience */ 52 vuint32 *regs; /* kernel's pointer to memory mapped registers */ 53 pci_info pcii; /* a convenience copy of the pci info for this device */ 54 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ 55}; 56 57typedef struct { 58 uint32 count; /* number of devices actually found */ 59 benaphore kernel; /* for serializing opens/closes */ 60 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ 61 device_info di[MAX_DEVICES]; /* device specific stuff */ 62} DeviceData; 63 64/* prototypes for our private functions */ 65static status_t open_hook(const char* name, uint32 flags, void** cookie); 66static status_t close_hook(void* dev); 67static status_t free_hook(void* dev); 68static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); 69static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); 70static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); 71static status_t map_device(device_info *di); 72static void unmap_device(device_info *di); 73static void probe_devices(void); 74static int32 nv_interrupt(void *data); 75 76static DeviceData *pd; 77static isa_module_info *isa_bus = NULL; 78static pci_module_info *pci_bus = NULL; 79static agp_gart_module_info *agp_bus = NULL; 80static device_hooks graphics_device_hooks = { 81 open_hook, 82 close_hook, 83 free_hook, 84 control_hook, 85 read_hook, 86 write_hook, 87 NULL, 88 NULL, 89 NULL, 90 NULL 91}; 92 93#define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ 94#define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ 95#define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ 96#define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ 97 98static uint16 nvidia_device_list[] = { 99 0x0020, /* Nvidia TNT1 */ 100 0x0028, /* Nvidia TNT2 (pro) */ 101 0x0029, /* Nvidia TNT2 Ultra */ 102 0x002a, /* Nvidia TNT2 */ 103 0x002b, /* Nvidia TNT2 */ 104 0x002c, /* Nvidia Vanta (Lt) */ 105 0x002d, /* Nvidia TNT2-M64 (Pro) */ 106 0x002e, /* Nvidia NV06 Vanta */ 107 0x002f, /* Nvidia NV06 Vanta */ 108 0x0040, /* Nvidia Geforce FX 6800 Ultra */ 109 0x0041, /* Nvidia Geforce FX 6800 */ 110 0x0042, /* Nvidia Geforce FX 6800LE */ 111 0x0043, /* Nvidia Geforce 6800 XE */ 112 0x0045, /* Nvidia Geforce FX 6800 GT */ 113 0x0046, /* Nvidia Geforce FX 6800 GT */ 114 0x0047, /* Nvidia Geforce 6800 GS */ 115 0x0048, /* Nvidia Geforce FX 6800 XT */ 116 0x0049, /* Nvidia unknown FX */ 117 0x004d, /* Nvidia Quadro FX 4400 */ 118 0x004e, /* Nvidia Quadro FX 4000 */ 119 0x0091, /* Nvidia Geforce 7800 GTX PCIe */ 120 0x0092, /* Nvidia Geforce 7800 GT PCIe */ 121 0x0098, /* Nvidia Geforce 7800 Go PCIe */ 122 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */ 123 0x009d, /* Nvidia Quadro FX 4500 */ 124 0x00a0, /* Nvidia Aladdin TNT2 */ 125 0x00c0, /* Nvidia Geforce 6800 GS */ 126 0x00c1, /* Nvidia Geforce FX 6800 */ 127 0x00c2, /* Nvidia Geforce FX 6800LE */ 128 0x00c3, /* Nvidia Geforce FX 6800 XT */ 129 0x00c8, /* Nvidia Geforce FX 6800 Go */ 130 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */ 131 0x00cc, /* Nvidia Quadro FX 1400 Go */ 132 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */ 133 0x00ce, /* Nvidia Quadro FX 1400 */ 134 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */ 135 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */ 136 0x00f2, /* Nvidia Geforce FX 6600 AGP */ 137 0x00f3, /* Nvidia Geforce 6200 */ 138 0x00f4, /* Nvidia Geforce 6600 LE */ 139 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */ 140 0x00f6, /* Nvidia Geforce 6800 GS */ 141 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */ 142 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */ 143 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */ 144 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */ 145 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */ 146 0x00fd, /* Nvidia Quadro PCX PCIe */ 147 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */ 148 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */ 149 0x0100, /* Nvidia Geforce256 SDR */ 150 0x0101, /* Nvidia Geforce256 DDR */ 151 0x0102, /* Nvidia Geforce256 Ultra */ 152 0x0103, /* Nvidia Quadro */ 153 0x0110, /* Nvidia Geforce2 MX/MX400 */ 154 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */ 155 0x0112, /* Nvidia Geforce2 Go */ 156 0x0113, /* Nvidia Quadro2 MXR/EX/Go */ 157 0x0140, /* Nvidia Geforce FX 6600 GT */ 158 0x0141, /* Nvidia Geforce FX 6600 */ 159 0x0142, /* Nvidia Geforce FX 6600LE */ 160 0x0143, /* Nvidia Geforce 6600 VE */ 161 0x0144, /* Nvidia Geforce FX 6600 Go */ 162 0x0145, /* Nvidia Geforce FX 6610 XL */ 163 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */ 164 0x0147, /* Nvidia Geforce FX 6700 XL */ 165 0x0148, /* Nvidia Geforce FX 6600 Go */ 166 0x0149, /* Nvidia Geforce FX 6600 GT Go */ 167 0x014b, /* Nvidia unknown FX */ 168 0x014c, /* Nvidia Quadro FX 540 MXM */ 169 0x014d, /* Nvidia unknown FX */ 170 0x014e, /* Nvidia Quadro FX 540 */ 171 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */ 172 0x0150, /* Nvidia Geforce2 GTS/Pro */ 173 0x0151, /* Nvidia Geforce2 Ti DDR */ 174 0x0152, /* Nvidia Geforce2 Ultra */ 175 0x0153, /* Nvidia Quadro2 Pro */ 176 0x0160, /* Nvidia Geforce 6500 Go */ 177 0x0161, /* Nvidia Geforce 6200 TurboCache */ 178 0x0162, /* Nvidia Geforce 6200SE TurboCache */ 179 0x0163, /* Nvidia Geforce 6200LE */ 180 0x0164, /* Nvidia Geforce FX 6200 Go */ 181 0x0165, /* Nvidia Quadro FX NVS 285 */ 182 0x0166, /* Nvidia Geforce 6400 Go */ 183 0x0167, /* Nvidia Geforce 6200 Go */ 184 0x0168, /* Nvidia Geforce 6400 Go */ 185 0x0169, /* Nvidia Geforce 6250 Go */ 186 0x016a, /* Nvidia Geforce 7100 GS */ 187 0x016b, /* Nvidia unknown FX Go */ 188 0x016c, /* Nvidia unknown FX Go */ 189 0x016d, /* Nvidia unknown FX Go */ 190 0x016e, /* Nvidia unknown FX */ 191 0x0170, /* Nvidia Geforce4 MX 460 */ 192 0x0171, /* Nvidia Geforce4 MX 440 */ 193 0x0172, /* Nvidia Geforce4 MX 420 */ 194 0x0173, /* Nvidia Geforce4 MX 440SE */ 195 0x0174, /* Nvidia Geforce4 440 Go */ 196 0x0175, /* Nvidia Geforce4 420 Go */ 197 0x0176, /* Nvidia Geforce4 420 Go 32M */ 198 0x0177, /* Nvidia Geforce4 460 Go */ 199 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 200 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */ 201 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 202 0x017c, /* Nvidia Quadro4 500 GoGL */ 203 0x017d, /* Nvidia Geforce4 410 Go 16M */ 204 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */ 205 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */ 206 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */ 207 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */ 208 0x0186, /* Nvidia Geforce4 448 Go */ 209 0x0187, /* Nvidia Geforce4 488 Go */ 210 0x0188, /* Nvidia Quadro4 580 XGL */ 211 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */ 212 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */ 213 0x018b, /* Nvidia Quadro4 380 XGL */ 214 0x018c, /* Nvidia Quadro4 NVS 50 PCI */ 215 0x018d, /* Nvidia Geforce4 448 Go */ 216 0x01a0, /* Nvidia Geforce2 Integrated GPU */ 217 0x01d1, /* Nvidia Geforce 7300 LE */ 218 0x01d3, /* Nvidia Geforce 7300 SE */ 219 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */ 220 0x01d8, /* Nvidia Geforce 7400 GO */ 221 0x01dd, /* Nvidia Geforce 7500 LE */ 222 0x01df, /* Nvidia Geforce 7300 GS */ 223 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */ 224 0x0200, /* Nvidia Geforce3 */ 225 0x0201, /* Nvidia Geforce3 Ti 200 */ 226 0x0202, /* Nvidia Geforce3 Ti 500 */ 227 0x0203, /* Nvidia Quadro DCC */ 228 0x0211, /* Nvidia Geforce FX 6800 */ 229 0x0212, /* Nvidia Geforce FX 6800LE */ 230 0x0215, /* Nvidia Geforce FX 6800 GT */ 231 0x0218, /* Nvidia Geforce 6800 XT */ 232 0x0220, /* Nvidia unknown FX */ 233 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */ 234 0x0222, /* Nvidia unknown FX */ 235 0x0228, /* Nvidia unknown FX Go */ 236 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */ 237 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */ 238 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */ 239 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */ 240 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */ 241 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */ 242 0x0250, /* Nvidia Geforce4 Ti 4600 */ 243 0x0251, /* Nvidia Geforce4 Ti 4400 */ 244 0x0252, /* Nvidia Geforce4 Ti 4600 */ 245 0x0253, /* Nvidia Geforce4 Ti 4200 */ 246 0x0258, /* Nvidia Quadro4 900 XGL */ 247 0x0259, /* Nvidia Quadro4 750 XGL */ 248 0x025b, /* Nvidia Quadro4 700 XGL */ 249 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */ 250 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */ 251 0x0282, /* Nvidia Geforce4 Ti 4800SE */ 252 0x0286, /* Nvidia Geforce4 4200 Go */ 253 0x0288, /* Nvidia Quadro4 980 XGL */ 254 0x0289, /* Nvidia Quadro4 780 XGL */ 255 0x028c, /* Nvidia Quadro4 700 GoGL */ 256 0x0290, /* Nvidia Geforce 7900 GTX */ 257 0x0291, /* Nvidia Geforce 7900 GT */ 258 0x0292, /* Nvidia Geforce 7900 GS */ 259 0x0293, /* Nvidia Geforce 7900 GX2 */ 260 0x0294, /* Nvidia Geforce 7950 GX2 */ 261 0x0295, /* Nvidia Geforce 7950 GT */ 262 0x0298, /* Nvidia Geforce Go 7900 GS */ 263 0x0299, /* Nvidia Geforce Go 7900 GTX */ 264 0x029c, /* Nvidia Quadro FX 5500 */ 265 0x029f, /* Nvidia Quadro FX 4500 X2 */ 266 0x02a0, /* Nvidia Geforce3 Integrated GPU */ 267 0x02e0, /* Nvidia Geforce 7600 GT */ 268 0x02e1, /* Nvidia Geforce 7600 GS */ 269 0x02e2, /* Nvidia Geforce 7300 GT */ 270 0x0301, /* Nvidia Geforce FX 5800 Ultra */ 271 0x0302, /* Nvidia Geforce FX 5800 */ 272 0x0308, /* Nvidia Quadro FX 2000 */ 273 0x0309, /* Nvidia Quadro FX 1000 */ 274 0x0311, /* Nvidia Geforce FX 5600 Ultra */ 275 0x0312, /* Nvidia Geforce FX 5600 */ 276 0x0313, /* Nvidia unknown FX */ 277 0x0314, /* Nvidia Geforce FX 5600XT */ 278 0x0316, /* Nvidia unknown FX Go */ 279 0x0317, /* Nvidia unknown FX Go */ 280 0x031a, /* Nvidia Geforce FX 5600 Go */ 281 0x031b, /* Nvidia Geforce FX 5650 Go */ 282 0x031c, /* Nvidia Quadro FX 700 Go */ 283 0x031d, /* Nvidia unknown FX Go */ 284 0x031e, /* Nvidia unknown FX Go */ 285 0x031f, /* Nvidia unknown FX Go */ 286 0x0320, /* Nvidia Geforce FX 5200 */ 287 0x0321, /* Nvidia Geforce FX 5200 Ultra */ 288 0x0322, /* Nvidia Geforce FX 5200 */ 289 0x0323, /* Nvidia Geforce FX 5200LE */ 290 0x0324, /* Nvidia Geforce FX 5200 Go */ 291 0x0325, /* Nvidia Geforce FX 5250 Go */ 292 0x0326, /* Nvidia Geforce FX 5500 */ 293 0x0327, /* Nvidia Geforce FX 5100 */ 294 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */ 295 0x0329, /* Nvidia Geforce FX 5200 (PPC) */ 296 0x032a, /* Nvidia Quadro NVS 280 PCI */ 297 0x032b, /* Nvidia Quadro FX 500/600 PCI */ 298 0x032c, /* Nvidia Geforce FX 5300 Go */ 299 0x032d, /* Nvidia Geforce FX 5100 Go */ 300 0x032e, /* Nvidia unknown FX Go */ 301 0x032f, /* Nvidia unknown FX Go */ 302 0x0330, /* Nvidia Geforce FX 5900 Ultra */ 303 0x0331, /* Nvidia Geforce FX 5900 */ 304 0x0332, /* Nvidia Geforce FX 5900 XT */ 305 0x0333, /* Nvidia Geforce FX 5950 Ultra */ 306 0x0334, /* Nvidia Geforce FX 5900 ZT */ 307 0x0338, /* Nvidia Quadro FX 3000 */ 308 0x033f, /* Nvidia Quadro FX 700 */ 309 0x0341, /* Nvidia Geforce FX 5700 Ultra */ 310 0x0342, /* Nvidia Geforce FX 5700 */ 311 0x0343, /* Nvidia Geforce FX 5700LE */ 312 0x0344, /* Nvidia Geforce FX 5700VE */ 313 0x0345, /* Nvidia unknown FX */ 314 0x0347, /* Nvidia Geforce FX 5700 Go */ 315 0x0348, /* Nvidia Geforce FX 5700 Go */ 316 0x0349, /* Nvidia unknown FX Go */ 317 0x034b, /* Nvidia unknown FX Go */ 318 0x034c, /* Nvidia Quadro FX 1000 Go */ 319 0x034e, /* Nvidia Quadro FX 1100 */ 320 0x034f, /* Nvidia unknown FX */ 321 0x0391, /* Nvidia Geforce 7600 GT */ 322 0x0392, /* Nvidia Geforce 7600 GS */ 323 0x0393, /* Nvidia Geforce 7300 GT */ 324 0x0394, /* Nvidia Geforce 7600 LE */ 325 0x0398, /* Nvidia Geforce 7600 GO */ 326 0x03d0, /* Nvidia Geforce 6100 nForce 430 */ 327 0x03d1, /* Nvidia Geforce 6100 nForce 405 */ 328 0x03d2, /* Nvidia Geforce 6100 nForce 400 */ 329 0x03d5, /* Nvidia Geforce 6100 nForce 420 */ 330 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */ 331 0x06e4, /* Nvidia Geforce 8400 GS G98 */ 332 0x06e8, /* Nvidia Geforce 9200M G98M */ 333 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */ 334 0 335}; 336 337static uint16 elsa_device_list[] = { 338 0x0c60, /* Elsa Gladiac Geforce2 MX */ 339 0 340}; 341 342static uint16 nvstbsgs_device_list[] = { 343 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */ 344 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */ 345 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */ 346 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */ 347 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */ 348 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */ 349 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */ 350 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 351 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */ 352 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */ 353 0 354}; 355 356static uint16 varisys_device_list[] = { 357 0x3503, /* Varisys Geforce4 MX440 */ 358 0x3505, /* Varisys Geforce4 Ti 4200 */ 359 0 360}; 361 362static struct { 363 uint16 vendor; 364 uint16 *devices; 365} SupportedDevices[] = { 366 {VENDOR_ID_NVIDIA, nvidia_device_list}, 367 {VENDOR_ID_ELSA, elsa_device_list}, 368 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list}, 369 {VENDOR_ID_VARISYS, varisys_device_list}, 370 {0x0000, NULL} 371}; 372 373static nv_settings sSettings = { // see comments in nvidia.settings 374 /* for driver */ 375 DRIVER_PREFIX ".accelerant", 376 "none", // primary 377 false, // dumprom 378 /* for accelerant */ 379 0x00000000, // logmask 380 0, // memory 381 0, // tv_output 382 true, // usebios 383 true, // hardcursor 384 false, // switchhead 385 false, // force_pci 386 false, // unhide_fw 387 false, // pgm_panel 388 true, // dma_acc 389 false, // vga_on_tv 390 false, // force_sync 391 false, // force_ws 392 false, // block_acc 393 0, // gpu_clk 394 0, // ram_clk 395 true, // check_edid 396}; 397 398 399static void 400dumprom(void *rom, uint32 size, pci_info pcii) 401{ 402 int fd; 403 uint32 cnt; 404 char fname[64]; 405 406 CALLED(); 407 /* determine the romfile name: we need split-up per card in the system */ 408 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", 409 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); 410 411 fd = open (fname, O_WRONLY | O_CREAT, 0666); 412 if (fd < 0) return; 413 414 /* apparantly max. 32kb may be written at once; 415 * the ROM size is a multiple of that anyway. */ 416 for (cnt = 0; (cnt < size); cnt += 32768) 417 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); 418 close (fd); 419} 420 421 422/*! return 1 if vblank interrupt has occured */ 423static int 424caused_vbi_crtc1(vuint32 * regs) 425{ 426 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); 427} 428 429 430/*! clear the vblank interrupt */ 431static void 432clear_vbi_crtc1(vuint32 * regs) 433{ 434 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 435} 436 437 438static void 439enable_vbi_crtc1(vuint32 * regs) 440{ 441 /* clear the vblank interrupt */ 442 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 443 /* enable nVidia interrupt source vblank */ 444 NV_REG32(NV32_CRTC_INTE) |= 0x00000001; 445 /* enable nVidia interrupt system hardware (b0-1) */ 446 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 447} 448 449 450static void 451disable_vbi_crtc1(vuint32 * regs) 452{ 453 /* disable nVidia interrupt source vblank */ 454 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 455 /* clear the vblank interrupt */ 456 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 457} 458 459 460/*! return 1 if vblank interrupt has occured */ 461static int 462caused_vbi_crtc2(vuint32 * regs) 463{ 464 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); 465} 466 467 468/*! clear the vblank interrupt */ 469static void 470clear_vbi_crtc2(vuint32 * regs) 471{ 472 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 473} 474 475 476static void 477enable_vbi_crtc2(vuint32 * regs) 478{ 479 /* clear the vblank interrupt */ 480 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 481 /* enable nVidia interrupt source vblank */ 482 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; 483 /* enable nVidia interrupt system hardware (b0-1) */ 484 NV_REG32(NV32_MAIN_INTE) = 0x00000001; 485} 486 487 488static void 489disable_vbi_crtc2(vuint32 * regs) 490{ 491 /* disable nVidia interrupt source vblank */ 492 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 493 /* clear the vblank interrupt */ 494 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 495} 496 497 498//fixme: 499//dangerous code, on singlehead cards better not try accessing secondary head 500//registers (card might react in unpredictable ways, though there's only a small 501//chance we actually run into this). 502//fix requires (some) card recognition code to be moved from accelerant to 503//kerneldriver... 504static void 505disable_vbi_all(vuint32 * regs) 506{ 507 /* disable nVidia interrupt source vblank */ 508 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; 509 /* clear the vblank interrupt */ 510 NV_REG32(NV32_CRTC_INTS) = 0x00000001; 511 512 /* disable nVidia interrupt source vblank */ 513 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; 514 /* clear the vblank interrupt */ 515 NV_REG32(NV32_CRTC2_INTS) = 0x00000001; 516 517 /* disable nVidia interrupt system hardware (b0-1) */ 518 NV_REG32(NV32_MAIN_INTE) = 0x00000000; 519} 520 521 522static status_t 523map_device(device_info *di) 524{ 525 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ 526 shared_info *si = di->si; 527 uint32 tmpUlong, tmpROMshadow; 528 pci_info *pcii = &(di->pcii); 529 phys_addr_t physicalAddress; 530 system_info sysinfo; 531 532 CALLED(); 533 /* variables for making copy of ROM */ 534 uint8* rom_temp; 535 area_id rom_area = -1; 536 537 /* Nvidia cards have registers in [0] and framebuffer in [1] */ 538 int registers = 0; 539 int frame_buffer = 1; 540 541 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ 542 tmpUlong = get_pci(PCI_command, 2); 543 /* enable PCI access */ 544 tmpUlong |= PCI_command_memory; 545 /* enable busmastering */ 546 tmpUlong |= PCI_command_master; 547 /* disable ISA I/O access */ 548 tmpUlong &= ~PCI_command_io; 549 set_pci(PCI_command, 2, tmpUlong); 550 551 /*work out which version of BeOS is running*/ 552 get_system_info(&sysinfo); 553 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ 554 { 555 si->use_clone_bugfix = 1; 556 } 557 else 558 { 559 si->use_clone_bugfix = 0; 560 } 561 562 /* work out a name for the register mapping */ 563 sprintf(buffer, DEVICE_FORMAT " regs", 564 di->pcii.vendor_id, di->pcii.device_id, 565 di->pcii.bus, di->pcii.device, di->pcii.function); 566 567 if ((di->pcii.u.h0.base_register_flags[registers] & PCI_address_type) 568 == PCI_address_type_64) { 569 TRACE("registers is 64 bit\n"); 570 } else { 571 TRACE("registers is 32 bit\n"); 572 } 573 574 /* get a virtual memory address for the registers*/ 575 si->regs_area = map_physical_memory( 576 buffer, 577 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ 578 di->pcii.u.h0.base_registers_pci[registers], 579 di->pcii.u.h0.base_register_sizes[registers], 580 B_ANY_KERNEL_ADDRESS, 581 B_CLONEABLE_AREA | B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 582 (void **)&(di->regs)); 583 si->clone_bugfix_regs = (uint32 *) di->regs; 584 585 /* if mapping registers to vmem failed then pass on error */ 586 if (si->regs_area < 0) return si->regs_area; 587 588 /* work out a name for the ROM mapping*/ 589 sprintf(buffer, DEVICE_FORMAT " rom", 590 di->pcii.vendor_id, di->pcii.device_id, 591 di->pcii.bus, di->pcii.device, di->pcii.function); 592 593 /* preserve ROM shadowing setting, we need to restore the current state later on. */ 594 /* warning: 595 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. 596 * NV18, NV28 and NV34 keep working. 597 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, 598 * however the actual ROM content (so the used part) is intact (confirmed). */ 599 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); 600 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ 601 set_pci(NVCFG_ROMSHADOW, 4, 0); 602 603 /* get ROM memory mapped base adress - this is defined in the PCI standard */ 604 tmpUlong = get_pci(PCI_rom_base, 4); 605 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not 606 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA 607 //legacy space will get us into trouble if we aren't the primary graphics card!! 608 //(as legacy space always has the primary card's ROM 'mapped'!) 609 if (tmpUlong) { 610 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ 611 tmpUlong |= 0x00000001; 612 set_pci(PCI_rom_base, 4, tmpUlong); 613 614 rom_area = map_physical_memory( 615 buffer, 616 di->pcii.u.h0.rom_base_pci, 617 di->pcii.u.h0.rom_size, 618 B_ANY_KERNEL_ADDRESS, 619 B_KERNEL_READ_AREA, 620 (void **)&(rom_temp) 621 ); 622 623 /* check if we got the BIOS and signature (might fail on laptops..) */ 624 if (rom_area >= 0) { 625 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { 626 /* apparantly no ROM is mapped here */ 627 delete_area(rom_area); 628 rom_area = -1; 629 /* force using ISA legacy map as fall-back */ 630 tmpUlong = 0x00000000; 631 } 632 } else { 633 /* mapping failed: force using ISA legacy map as fall-back */ 634 tmpUlong = 0x00000000; 635 } 636 } 637 638 if (!tmpUlong) { 639 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ 640 rom_area = map_physical_memory(buffer, 0x000c0000, 641 65536, B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA, (void **)&(rom_temp)); 642 } 643 644 /* if mapping ROM to vmem failed then clean up and pass on error */ 645 if (rom_area < 0) { 646 delete_area(si->regs_area); 647 si->regs_area = -1; 648 return rom_area; 649 } 650 651 /* dump ROM to file if selected in nvidia.settings 652 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ 653 if (sSettings.dumprom) 654 dumprom(rom_temp, 65536, di->pcii); 655 656 /* make a copy of ROM for future reference */ 657 memcpy(si->rom_mirror, rom_temp, 65536); 658 659 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ 660 tmpUlong = get_pci(PCI_rom_base, 4); 661 tmpUlong &= 0xfffffffe; 662 set_pci(PCI_rom_base, 4, tmpUlong); 663 delete_area(rom_area); 664 665 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ 666 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); 667 668 /* work out a name for the framebuffer mapping*/ 669 sprintf(buffer, DEVICE_FORMAT " framebuffer", 670 di->pcii.vendor_id, di->pcii.device_id, 671 di->pcii.bus, di->pcii.device, di->pcii.function); 672 673 physicalAddress = di->pcii.u.h0.base_registers_pci[frame_buffer]; 674 if ((di->pcii.u.h0.base_register_flags[frame_buffer] & PCI_address_type) 675 == PCI_address_type_64) { 676 TRACE("framebuffer is 64 bit\n"); 677 physicalAddress 678 |= (uint64)di->pcii.u.h0.base_registers_pci[frame_buffer + 1] << 32; 679 } else { 680 TRACE("framebuffer is 32 bit\n"); 681 } 682 683 /* map the framebuffer into vmem, using Write Combining*/ 684 si->fb_area = map_physical_memory(buffer, 685 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 686 physicalAddress, 687 di->pcii.u.h0.base_register_sizes[frame_buffer], 688 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 689 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA, 690 &(si->framebuffer)); 691 692 /*if failed with write combining try again without*/ 693 if (si->fb_area < 0) { 694 si->fb_area = map_physical_memory(buffer, 695 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ 696 physicalAddress, 697 di->pcii.u.h0.base_register_sizes[frame_buffer], 698 B_ANY_KERNEL_BLOCK_ADDRESS, 699 B_READ_AREA | B_WRITE_AREA | B_CLONEABLE_AREA, 700 &(si->framebuffer)); 701 } 702 703 /* if there was an error, delete our other areas and pass on error*/ 704 if (si->fb_area < 0) { 705 delete_area(si->regs_area); 706 si->regs_area = -1; 707 return si->fb_area; 708 } 709 710 //fixme: retest for card coldstart and PCI/virt_mem mapping!! 711 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ 712 si->framebuffer_pci = (void *) physicalAddress; 713 714 /* note the amount of memory mapped by the kerneldriver so we can make sure we 715 * don't attempt to adress more later on */ 716 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer]; 717 718 // remember settings for use here and in accelerant 719 si->settings = sSettings; 720 721 if (si->fb_area >= 0) { 722 TRACE("framebuffer mapped OK\n"); 723 } else { 724 TRACE("framebuffer mapping failed!\n"); 725 } 726 727 /* in any case, return the result */ 728 return si->fb_area; 729} 730 731 732static void 733unmap_device(device_info *di) 734{ 735 shared_info *si = di->si; 736 uint32 tmpUlong; 737 pci_info *pcii = &(di->pcii); 738 739 CALLED(); 740 /* disable memory mapped IO */ 741 tmpUlong = get_pci(PCI_command, 4); 742 tmpUlong &= 0xfffffffc; 743 set_pci(PCI_command, 4, tmpUlong); 744 /* delete the areas */ 745 if (si->regs_area >= 0) 746 delete_area(si->regs_area); 747 if (si->fb_area >= 0) 748 delete_area(si->fb_area); 749 si->regs_area = si->fb_area = -1; 750 si->framebuffer = NULL; 751 di->regs = NULL; 752} 753 754 755static void 756probe_devices(void) 757{ 758 uint32 pci_index = 0; 759 uint32 count = 0; 760 device_info *di = pd->di; 761 char tmp_name[B_OS_NAME_LENGTH]; 762 763 CALLED(); 764 /* while there are more pci devices */ 765 while (count < MAX_DEVICES 766 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { 767 int vendor = 0; 768 769 /* if we match a supported vendor */ 770 while (SupportedDevices[vendor].vendor) { 771 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { 772 uint16 *devices = SupportedDevices[vendor].devices; 773 /* while there are more supported devices */ 774 while (*devices) { 775 /* if we match a supported device */ 776 if (*devices == di->pcii.device_id ) { 777 /* publish the device name */ 778 sprintf(tmp_name, DEVICE_FORMAT, 779 di->pcii.vendor_id, di->pcii.device_id, 780 di->pcii.bus, di->pcii.device, di->pcii.function); 781 /* tweak the exported name to show first in the alphabetically ordered /dev/ 782 * hierarchy folder, so the system will use it as primary adaptor if requested 783 * via nvidia.settings. */ 784 if (strcmp(tmp_name, sSettings.primary) == 0) 785 sprintf(tmp_name, "-%s", sSettings.primary); 786 /* add /dev/ hierarchy path */ 787 sprintf(di->name, "graphics/%s", tmp_name); 788 /* remember the name */ 789 pd->device_names[count] = di->name; 790 /* mark the driver as available for R/W open */ 791 di->is_open = 0; 792 /* mark areas as not yet created */ 793 di->shared_area = -1; 794 /* mark pointer to shared data as invalid */ 795 di->si = NULL; 796 /* inc pointer to device info */ 797 di++; 798 /* inc count */ 799 count++; 800 /* break out of these while loops */ 801 goto next_device; 802 } 803 /* next supported device */ 804 devices++; 805 } 806 } 807 vendor++; 808 } 809next_device: 810 /* next pci_info struct, please */ 811 pci_index++; 812 } 813 /* propagate count */ 814 pd->count = count; 815 /* terminate list of device names with a null pointer */ 816 pd->device_names[pd->count] = NULL; 817} 818 819 820static uint32 821thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) 822{ 823 uint32 handled = B_HANDLED_INTERRUPT; 824 /* release the vblank semaphore */ 825 if (si->vblank >= 0) { 826 int32 blocked; 827 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { 828 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); 829 handled = B_INVOKE_SCHEDULER; 830 } 831 } 832 return handled; 833} 834 835 836static int32 837nv_interrupt(void *data) 838{ 839 int32 handled = B_UNHANDLED_INTERRUPT; 840 device_info *di = (device_info *)data; 841 shared_info *si = di->si; 842 int32 *flags = &(si->flags); 843 vuint32 *regs; 844 845 /* is someone already handling an interrupt for this device? */ 846 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; 847 848 /* get regs */ 849 regs = di->regs; 850 851 /* was it a VBI? */ 852 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ 853 if (si->ps.secondary_head) { 854 //fixme: 855 //rewrite once we use one driver instance 'per head' (instead of 'per card') 856 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { 857 /* clear the interrupt(s) */ 858 clear_vbi_crtc1(regs); 859 clear_vbi_crtc2(regs); 860 /* release the semaphore */ 861 handled = thread_interrupt_work(flags, regs, si); 862 } 863 } else { 864 if (caused_vbi_crtc1(regs)) { 865 /* clear the interrupt */ 866 clear_vbi_crtc1(regs); 867 /* release the semaphore */ 868 handled = thread_interrupt_work(flags, regs, si); 869 } 870 } 871 872 /* note that we're not in the handler any more */ 873 atomic_and(flags, ~SKD_HANDLER_INSTALLED); 874 875exit0: 876 return handled; 877} 878 879 880// #pragma mark - device hooks 881 882 883static status_t 884open_hook(const char* name, uint32 flags, void** cookie) 885{ 886 int32 index = 0; 887 device_info *di; 888 shared_info *si; 889 thread_id thid; 890 thread_info thinfo; 891 status_t result = B_OK; 892 char shared_name[B_OS_NAME_LENGTH]; 893 physical_entry map[1]; 894 size_t net_buf_size; 895 void *unaligned_dma_buffer; 896 uint32 mem_size; 897 898 CALLED(); 899 /* find the device name in the list of devices */ 900 /* we're never passed a name we didn't publish */ 901 while (pd->device_names[index] 902 && (strcmp(name, pd->device_names[index]) != 0)) 903 index++; 904 905 /* for convienience */ 906 di = &(pd->di[index]); 907 908 /* make sure no one else has write access to the common data */ 909 AQUIRE_BEN(pd->kernel); 910 911 /* if it's already open for writing */ 912 if (di->is_open) { 913 /* mark it open another time */ 914 goto mark_as_open; 915 } 916 /* create the shared_info area */ 917 sprintf(shared_name, DEVICE_FORMAT " shared", 918 di->pcii.vendor_id, di->pcii.device_id, 919 di->pcii.bus, di->pcii.device, di->pcii.function); 920 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, 921 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, 922 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA | B_CLONEABLE_AREA); 923 if (di->shared_area < 0) { 924 /* return the error */ 925 result = di->shared_area; 926 goto done; 927 } 928 929 /* save a few dereferences */ 930 si = di->si; 931 932 /* create the DMA command buffer area */ 933 //fixme? for R4.5 a workaround for cloning would be needed! 934 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ 935 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); 936 /* create the area that will hold the DMA command buffer */ 937 si->unaligned_dma_area = 938 create_area("NV DMA cmd buffer", 939 (void **)&unaligned_dma_buffer, 940 B_ANY_KERNEL_ADDRESS, 941 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ 942 B_32_BIT_CONTIGUOUS, /* GPU always needs access */ 943 B_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); 944 // TODO: Physical aligning can be done without waste using the 945 // private create_area_etc(). 946 /* on error, abort */ 947 if (si->unaligned_dma_area < 0) 948 { 949 /* free the already created shared_info area, and return the error */ 950 result = si->unaligned_dma_area; 951 goto free_shared; 952 } 953 /* we (also) need the physical adress our DMA buffer is at, as this needs to be 954 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC 955 * even on older CPU's. */ 956 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); 957 si->dma_buffer_pci = (void*) 958 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); 959 960 /* map the net DMA command buffer into vmem, using Write Combining */ 961 si->dma_area = map_physical_memory( 962 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, 963 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 964 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 965 /* if failed with write combining try again without */ 966 if (si->dma_area < 0) { 967 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer", 968 (addr_t)si->dma_buffer_pci, net_buf_size, 969 B_ANY_KERNEL_BLOCK_ADDRESS, 970 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); 971 } 972 /* if there was an error, delete our other areas and pass on error*/ 973 if (si->dma_area < 0) 974 { 975 /* free the already created areas, and return the error */ 976 result = si->dma_area; 977 goto free_shared_and_uadma; 978 } 979 980 /* save the vendor and device IDs */ 981 si->vendor_id = di->pcii.vendor_id; 982 si->device_id = di->pcii.device_id; 983 si->revision = di->pcii.revision; 984 si->bus = di->pcii.bus; 985 si->device = di->pcii.device; 986 si->function = di->pcii.function; 987 988 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ 989 si->accelerant_in_use = false; 990 /* preset singlehead card to prevent early INT routine calls (once installed) to 991 * wrongly identify the INT request coming from us! */ 992 si->ps.secondary_head = false; 993 994 /* map the device */ 995 result = map_device(di); 996 if (result < 0) goto free_shared_and_alldma; 997 998 /* we will be returning OK status for sure now */ 999 result = B_OK; 1000 1001 /* note the amount of system RAM the system BIOS assigned to the card if applicable: 1002 * unified memory architecture (UMA) */ 1003 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) 1004 { 1005 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */ 1006 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ 1007 mem_size = 1024 * 1024 * 1008 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); 1009 /* don't attempt to adress memory not mapped by the kerneldriver */ 1010 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 1011 /* last 64kB RAM is used for the BIOS (or something else?) */ 1012 si->ps.memory_size -= (64 * 1024); 1013 break; 1014 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */ 1015 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ 1016 mem_size = 1024 * 1024 * 1017 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); 1018 /* don't attempt to adress memory not mapped by the kerneldriver */ 1019 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 1020 /* last 64kB RAM is used for the BIOS (or something else?) */ 1021 si->ps.memory_size -= (64 * 1024); 1022 break; 1023 default: 1024 /* all other cards have own RAM: the amount of which is determined in the 1025 * accelerant. */ 1026 break; 1027 } 1028 1029 /* disable and clear any pending interrupts */ 1030 //fixme: 1031 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1032 disable_vbi_all(di->regs); 1033 1034 /* preset we can't use INT related functions */ 1035 si->ps.int_assigned = false; 1036 1037 /* create a semaphore for vertical blank management */ 1038 si->vblank = create_sem(0, di->name); 1039 if (si->vblank < 0) goto mark_as_open; 1040 1041 /* change the owner of the semaphores to the opener's team */ 1042 /* this is required because apps can't aquire kernel semaphores */ 1043 thid = find_thread(NULL); 1044 get_thread_info(thid, &thinfo); 1045 set_sem_owner(si->vblank, thinfo.team); 1046 1047 /* If there is a valid interrupt line assigned then set up interrupts */ 1048 if ((di->pcii.u.h0.interrupt_pin == 0x00) || 1049 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ 1050 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ 1051 { 1052 /* delete the semaphore as it won't be used */ 1053 delete_sem(si->vblank); 1054 si->vblank = -1; 1055 } 1056 else 1057 { 1058 /* otherwise install our interrupt handler */ 1059 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); 1060 /* bail if we couldn't install the handler */ 1061 if (result != B_OK) 1062 { 1063 /* delete the semaphore as it won't be used */ 1064 delete_sem(si->vblank); 1065 si->vblank = -1; 1066 } 1067 else 1068 { 1069 /* inform accelerant(s) we can use INT related functions */ 1070 si->ps.int_assigned = true; 1071 } 1072 } 1073 1074mark_as_open: 1075 /* mark the device open */ 1076 di->is_open++; 1077 1078 /* send the cookie to the opener */ 1079 *cookie = di; 1080 1081 TRACE("open_hook: device is open\n"); 1082 goto done; 1083 1084 1085free_shared_and_alldma: 1086 /* clean up our aligned DMA area */ 1087 delete_area(si->dma_area); 1088 si->dma_area = -1; 1089 si->dma_buffer = NULL; 1090 1091free_shared_and_uadma: 1092 /* clean up our unaligned DMA area */ 1093 delete_area(si->unaligned_dma_area); 1094 si->unaligned_dma_area = -1; 1095 si->dma_buffer_pci = NULL; 1096 1097free_shared: 1098 /* clean up our shared area */ 1099 delete_area(di->shared_area); 1100 di->shared_area = -1; 1101 di->si = NULL; 1102 TRACE("open_hook: device is freed\n"); 1103 1104done: 1105 /* end of critical section */ 1106 RELEASE_BEN(pd->kernel); 1107 1108 /* all done, return the status */ 1109 return result; 1110} 1111 1112 1113static status_t 1114read_hook(void* dev, off_t pos, void* buf, size_t* len) 1115{ 1116 *len = 0; 1117 return B_NOT_ALLOWED; 1118} 1119 1120 1121static status_t 1122write_hook(void* dev, off_t pos, const void* buf, size_t* len) 1123{ 1124 *len = 0; 1125 return B_NOT_ALLOWED; 1126} 1127 1128 1129static status_t 1130close_hook(void* dev) 1131{ 1132 CALLED(); 1133 /* we don't do anything on close: there might be dup'd fd */ 1134 return B_NO_ERROR; 1135} 1136 1137 1138static status_t 1139free_hook(void* dev) 1140{ 1141 device_info *di = (device_info *)dev; 1142 shared_info *si = di->si; 1143 vuint32 *regs = di->regs; 1144 1145 CALLED(); 1146 /* lock the driver */ 1147 AQUIRE_BEN(pd->kernel); 1148 1149 /* if opened multiple times, decrement the open count and exit */ 1150 if (di->is_open > 1) 1151 goto unlock_and_exit; 1152 1153 /* disable and clear any pending interrupts */ 1154 //fixme: 1155 //distinquish between crtc1/crtc2 once all heads get seperate driver instances! 1156 disable_vbi_all(regs); 1157 1158 if (si->ps.int_assigned) { 1159 /* remove interrupt handler */ 1160 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); 1161 1162 /* delete the semaphores, ignoring any errors ('cause the owning 1163 team may have died on us) */ 1164 delete_sem(si->vblank); 1165 si->vblank = -1; 1166 } 1167 1168 /* free regs and framebuffer areas */ 1169 unmap_device(di); 1170 1171 /* clean up our aligned DMA area */ 1172 delete_area(si->dma_area); 1173 si->dma_area = -1; 1174 si->dma_buffer = NULL; 1175 1176 /* clean up our unaligned DMA area */ 1177 delete_area(si->unaligned_dma_area); 1178 si->unaligned_dma_area = -1; 1179 si->dma_buffer_pci = NULL; 1180 1181 /* clean up our shared area */ 1182 delete_area(di->shared_area); 1183 di->shared_area = -1; 1184 di->si = NULL; 1185 1186unlock_and_exit: 1187 /* mark the device available */ 1188 di->is_open--; 1189 /* unlock the driver */ 1190 RELEASE_BEN(pd->kernel); 1191 /* all done */ 1192 return B_OK; 1193} 1194 1195 1196static status_t 1197control_hook(void* dev, uint32 msg, void *buf, size_t len) 1198{ 1199 device_info *di = (device_info *)dev; 1200 status_t result = B_DEV_INVALID_IOCTL; 1201 uint32 tmpUlong; 1202 1203 switch (msg) { 1204 /* the only PUBLIC ioctl */ 1205 case B_GET_ACCELERANT_SIGNATURE: { 1206 TRACE("return signature\n"); 1207 if (user_strlcpy((char* )buf, sSettings.accelerant, len) < B_OK) 1208 return B_BAD_ADDRESS; 1209 result = B_OK; 1210 break; 1211 } 1212 1213 /* PRIVATE ioctl from here on */ 1214 case NV_GET_PRIVATE_DATA: { 1215 TRACE("return private data\n"); 1216 nv_get_private_data gpd; 1217 if (user_memcpy(&gpd, buf, sizeof(nv_get_private_data)) < B_OK) 1218 return B_BAD_ADDRESS; 1219 if (gpd.magic == NV_PRIVATE_DATA_MAGIC) { 1220 gpd.shared_info_area = di->shared_area; 1221 result = user_memcpy(buf, &gpd, sizeof(nv_get_private_data)); 1222 } 1223 break; 1224 } 1225 case NV_GET_PCI: { 1226 nv_get_set_pci gsp; 1227 if (user_memcpy(&gsp, buf, sizeof(nv_get_set_pci)) < B_OK) 1228 return B_BAD_ADDRESS; 1229 if (gsp.magic == NV_PRIVATE_DATA_MAGIC) { 1230 pci_info *pcii = &(di->pcii); 1231 gsp.value = get_pci(gsp.offset, gsp.size); 1232 result = user_memcpy(buf, &gsp, sizeof(nv_get_set_pci)); 1233 } 1234 break; 1235 } 1236 case NV_SET_PCI: { 1237 nv_get_set_pci gsp; 1238 if (user_memcpy(&gsp, buf, sizeof(nv_get_set_pci)) < B_OK) 1239 return B_BAD_ADDRESS; 1240 if (gsp.magic == NV_PRIVATE_DATA_MAGIC) { 1241 pci_info *pcii = &(di->pcii); 1242 set_pci(gsp.offset, gsp.size, gsp.value); 1243 result = B_OK; 1244 } 1245 break; 1246 } 1247 case NV_DEVICE_NAME: { 1248 TRACE("return device name\n"); 1249 nv_device_name dn; 1250 if (user_memcpy(&dn, buf, sizeof(nv_device_name)) < B_OK) 1251 return B_BAD_ADDRESS; 1252 if (dn.magic == NV_PRIVATE_DATA_MAGIC) { 1253 if (user_strlcpy(dn.name, di->name, B_OS_NAME_LENGTH) < B_OK) 1254 return B_BAD_ADDRESS; 1255 result = B_OK; 1256 } 1257 break; 1258 } 1259 case NV_RUN_INTERRUPTS: { 1260 nv_set_vblank_int vi; 1261 if (user_memcpy(&vi, buf, sizeof(nv_set_vblank_int)) < B_OK) 1262 return B_BAD_ADDRESS; 1263 if (vi.magic == NV_PRIVATE_DATA_MAGIC) { 1264 vuint32 *regs = di->regs; 1265 if (!(vi.crtc)) { 1266 if (vi.do_it) { 1267 enable_vbi_crtc1(regs); 1268 } else { 1269 disable_vbi_crtc1(regs); 1270 } 1271 } else { 1272 if (vi.do_it) { 1273 enable_vbi_crtc2(regs); 1274 } else { 1275 disable_vbi_crtc2(regs); 1276 } 1277 } 1278 result = B_OK; 1279 } 1280 break; 1281 } 1282 case NV_GET_NTH_AGP_INFO: { 1283 nv_nth_agp_info nai; 1284 if (user_memcpy(&nai, buf, sizeof(nv_nth_agp_info)) < B_OK) 1285 return B_BAD_ADDRESS; 1286 if (nai.magic == NV_PRIVATE_DATA_MAGIC) { 1287 nai.exist = false; 1288 nai.agp_bus = false; 1289 if (agp_bus) { 1290 nai.agp_bus = true; 1291 if ((*agp_bus->get_nth_agp_info)(nai.index, &(nai.agpi)) == B_NO_ERROR) { 1292 nai.exist = true; 1293 } 1294 } 1295 result = user_memcpy(buf, &nai, sizeof(nv_nth_agp_info)); 1296 } 1297 break; 1298 } 1299 case NV_ENABLE_AGP: { 1300 nv_cmd_agp nca; 1301 if (user_memcpy(&nca, buf, sizeof(nv_cmd_agp)) < B_OK) 1302 return B_BAD_ADDRESS; 1303 if (nca.magic == NV_PRIVATE_DATA_MAGIC) { 1304 if (agp_bus) { 1305 nca.agp_bus = true; 1306 nca.cmd = agp_bus->set_agp_mode(nca.cmd); 1307 } else { 1308 nca.agp_bus = false; 1309 nca.cmd = 0; 1310 } 1311 result = user_memcpy(buf, &nca, sizeof(nv_cmd_agp)); 1312 } 1313 break; 1314 } 1315 case NV_ISA_OUT: { 1316 nv_in_out_isa io_isa; 1317 if (user_memcpy(&io_isa, buf, sizeof(nv_in_out_isa)) < B_OK) 1318 return B_BAD_ADDRESS; 1319 if (io_isa.magic == NV_PRIVATE_DATA_MAGIC) { 1320 pci_info *pcii = &(di->pcii); 1321 1322 /* lock the driver: 1323 * no other graphics card may have ISA I/O enabled when we enter */ 1324 AQUIRE_BEN(pd->kernel); 1325 1326 /* enable ISA I/O access */ 1327 tmpUlong = get_pci(PCI_command, 2); 1328 tmpUlong |= PCI_command_io; 1329 set_pci(PCI_command, 2, tmpUlong); 1330 1331 if (io_isa.size == 1) 1332 isa_bus->write_io_8(io_isa.adress, (uint8)io_isa.data); 1333 else 1334 isa_bus->write_io_16(io_isa.adress, io_isa.data); 1335 result = B_OK; 1336 1337 /* disable ISA I/O access */ 1338 tmpUlong = get_pci(PCI_command, 2); 1339 tmpUlong &= ~PCI_command_io; 1340 set_pci(PCI_command, 2, tmpUlong); 1341 1342 /* end of critical section */ 1343 RELEASE_BEN(pd->kernel); 1344 } 1345 break; 1346 } 1347 case NV_ISA_IN: { 1348 nv_in_out_isa io_isa; 1349 if (user_memcpy(&io_isa, buf, sizeof(nv_in_out_isa)) < B_OK) 1350 return B_BAD_ADDRESS; 1351 if (io_isa.magic == NV_PRIVATE_DATA_MAGIC) { 1352 pci_info *pcii = &(di->pcii); 1353 1354 /* lock the driver: 1355 * no other graphics card may have ISA I/O enabled when we enter */ 1356 AQUIRE_BEN(pd->kernel); 1357 1358 /* enable ISA I/O access */ 1359 tmpUlong = get_pci(PCI_command, 2); 1360 tmpUlong |= PCI_command_io; 1361 set_pci(PCI_command, 2, tmpUlong); 1362 1363 if (io_isa.size == 1) 1364 io_isa.data = isa_bus->read_io_8(io_isa.adress); 1365 else 1366 io_isa.data = isa_bus->read_io_16(io_isa.adress); 1367 result = user_memcpy(buf, &io_isa, sizeof(nv_in_out_isa)); 1368 1369 /* disable ISA I/O access */ 1370 tmpUlong = get_pci(PCI_command, 2); 1371 tmpUlong &= ~PCI_command_io; 1372 set_pci(PCI_command, 2, tmpUlong); 1373 1374 /* end of critical section */ 1375 RELEASE_BEN(pd->kernel); 1376 } 1377 break; 1378 } 1379 } 1380 1381 return result; 1382} 1383 1384 1385// #pragma mark - driver API 1386 1387 1388status_t 1389init_hardware(void) 1390{ 1391 long index = 0; 1392 pci_info pcii; 1393 bool found = false; 1394 1395 CALLED(); 1396 /* choke if we can't find the PCI bus */ 1397 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1398 return B_ERROR; 1399 1400 /* choke if we can't find the ISA bus */ 1401 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) 1402 { 1403 put_module(B_PCI_MODULE_NAME); 1404 return B_ERROR; 1405 } 1406 1407 /* while there are more pci devices */ 1408 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { 1409 int vendor = 0; 1410 1411 /* if we match a supported vendor */ 1412 while (SupportedDevices[vendor].vendor) { 1413 if (SupportedDevices[vendor].vendor == pcii.vendor_id) { 1414 uint16 *devices = SupportedDevices[vendor].devices; 1415 /* while there are more supported devices */ 1416 while (*devices) { 1417 /* if we match a supported device */ 1418 if (*devices == pcii.device_id ) { 1419 1420 found = true; 1421 goto done; 1422 } 1423 /* next supported device */ 1424 devices++; 1425 } 1426 } 1427 vendor++; 1428 } 1429 /* next pci_info struct, please */ 1430 index++; 1431 } 1432 1433done: 1434 if (found) { 1435 TRACE ("init_hardware: found device\n"); 1436 } else { 1437 TRACE ("init_hardware: no supported device found\n"); 1438 } 1439 1440 /* put away the module manager */ 1441 put_module(B_PCI_MODULE_NAME); 1442 return found ? B_OK : B_ERROR; 1443} 1444 1445 1446status_t 1447init_driver(void) 1448{ 1449 void *settings; 1450 1451 CALLED(); 1452 // get driver/accelerant settings 1453 settings = load_driver_settings(DRIVER_PREFIX ".settings"); 1454 if (settings != NULL) { 1455 const char *item; 1456 char *end; 1457 uint32 value; 1458 1459 TRACE("init_driver: nvidia.settings loaded\n"); 1460 // for driver 1461 item = get_driver_parameter(settings, "accelerant", "", ""); 1462 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) 1463 strcpy (sSettings.accelerant, item); 1464 1465 item = get_driver_parameter(settings, "primary", "", ""); 1466 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) 1467 strcpy(sSettings.primary, item); 1468 1469 sSettings.dumprom = get_driver_boolean_parameter(settings, 1470 "dumprom", false, false); 1471 1472 if (sSettings.dumprom) { 1473 TRACE("dumprom requested\n"); 1474 } else { 1475 TRACE("no dumprom requested\n"); 1476 } 1477 1478 // for accelerant 1479 item = get_driver_parameter(settings, "logmask", 1480 "0x00000000", "0x00000000"); 1481 value = strtoul(item, &end, 0); 1482 if (*end == '\0') 1483 sSettings.logmask = value; 1484 1485 item = get_driver_parameter(settings, "memory", "0", "0"); 1486 value = strtoul(item, &end, 0); 1487 if (*end == '\0') 1488 sSettings.memory = value; 1489 1490 item = get_driver_parameter(settings, "tv_output", "0", "0"); 1491 value = strtoul(item, &end, 0); 1492 if (*end == '\0') 1493 sSettings.tv_output = value; 1494 1495 sSettings.hardcursor = get_driver_boolean_parameter(settings, 1496 "hardcursor", true, true); 1497 sSettings.usebios = get_driver_boolean_parameter(settings, 1498 "usebios", true, true); 1499 sSettings.switchhead = get_driver_boolean_parameter(settings, 1500 "switchhead", false, false); 1501 sSettings.force_pci = get_driver_boolean_parameter(settings, 1502 "force_pci", false, false); 1503 sSettings.unhide_fw = get_driver_boolean_parameter(settings, 1504 "unhide_fw", false, false); 1505 sSettings.pgm_panel = get_driver_boolean_parameter(settings, 1506 "pgm_panel", false, false); 1507 sSettings.dma_acc = get_driver_boolean_parameter(settings, 1508 "dma_acc", true, true); 1509 sSettings.vga_on_tv = get_driver_boolean_parameter(settings, 1510 "vga_on_tv", false, false); 1511 sSettings.force_sync = get_driver_boolean_parameter(settings, 1512 "force_sync", false, false); 1513 sSettings.force_ws = get_driver_boolean_parameter(settings, 1514 "force_ws", false, false); 1515 sSettings.block_acc = get_driver_boolean_parameter(settings, 1516 "block_acc", false, false); 1517 sSettings.check_edid = get_driver_boolean_parameter(settings, 1518 "check_edid", true, true); 1519 1520 item = get_driver_parameter(settings, "gpu_clk", "0", "0"); 1521 value = strtoul(item, &end, 0); 1522 if (*end == '\0') 1523 sSettings.gpu_clk = value; 1524 1525 item = get_driver_parameter(settings, "ram_clk", "0", "0"); 1526 value = strtoul(item, &end, 0); 1527 if (*end == '\0') 1528 sSettings.ram_clk = value; 1529 1530 unload_driver_settings(settings); 1531 } 1532 1533 /* get a handle for the pci bus */ 1534 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) 1535 return B_ERROR; 1536 1537 /* get a handle for the isa bus */ 1538 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { 1539 put_module(B_PCI_MODULE_NAME); 1540 return B_ERROR; 1541 } 1542 1543 /* get a handle for the agp bus if it exists */ 1544 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus); 1545 1546 /* driver private data */ 1547 pd = (DeviceData *)calloc(1, sizeof(DeviceData)); 1548 if (!pd) { 1549 put_module(B_PCI_MODULE_NAME); 1550 return B_ERROR; 1551 } 1552 /* initialize the benaphore */ 1553 INIT_BEN(pd->kernel); 1554 /* find all of our supported devices */ 1555 probe_devices(); 1556 1557 TRACE("init_driver: completed OK\n"); 1558 return B_OK; 1559} 1560 1561 1562const char ** 1563publish_devices(void) 1564{ 1565 CALLED(); 1566 /* return the list of supported devices */ 1567 return (const char **)pd->device_names; 1568} 1569 1570 1571device_hooks * 1572find_device(const char *name) 1573{ 1574 int index = 0; 1575 while (pd->device_names[index]) { 1576 if (strcmp(name, pd->device_names[index]) == 0) 1577 return &graphics_device_hooks; 1578 index++; 1579 } 1580 return NULL; 1581 1582} 1583 1584 1585void 1586uninit_driver(void) 1587{ 1588 CALLED(); 1589 /* free the driver data */ 1590 DELETE_BEN(pd->kernel); 1591 free(pd); 1592 pd = NULL; 1593 1594 /* put the pci module away */ 1595 put_module(B_PCI_MODULE_NAME); 1596 put_module(B_ISA_MODULE_NAME); 1597 1598 /* put the agp module away if it's there */ 1599 if (agp_bus) 1600 put_module(B_AGP_GART_MODULE_NAME); 1601} 1602 1603