/haiku/src/add-ons/accelerants/via/engine/ |
H A D | info.c | 257 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 258 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 284 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 285 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 313 ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && 330 if (DACR(FP_TG_CTRL) & 0x80000000) 358 si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; 359 si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; 360 si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; 362 si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_ [all...] |
H A D | crtc.c | 338 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 343 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 362 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 407 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 408 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 409 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 410 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 411 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 412 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 413 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG [all...] |
H A D | dac.c | 22 output = DACR(OUTPUT); 24 dac = DACR(TSTCTRL); 27 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 33 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 38 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 43 if (DACR(TSTCTRL) & 0x10000000) 55 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
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H A D | dac2.c | 43 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 61 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
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/haiku/src/add-ons/accelerants/nvidia/engine/ |
H A D | nv_dac.c | 21 output = DACR(OUTPUT); 23 dac = DACR(TSTCTRL); 26 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 44 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 49 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 54 if (DACR(TSTCTRL) & 0x10000000) 66 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 119 DACW(NV11_DITHER, (DACR(NV11_DITHER) | 0x00010000)); 130 DACW(FP_DITHER, (DACR(FP_DITHER) | 0x00000001)); 137 DACW(NV11_DITHER, (DACR(NV11_DITHE [all...] |
H A D | nv_crtc.c | 475 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 480 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 499 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 544 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 545 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 546 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 547 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 548 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 549 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 550 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG [all...] |
H A D | nv_dac2.c | 54 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 72 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 183 LOG(4,("DAC2: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP))); 193 DACW(NV30_PLLSETUP, (DACR(NV30_PLLSETUP) & ~0x000000f0)); 224 DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100));
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H A D | nv_info.c | 2330 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2331 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2357 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2358 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2387 ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && 2404 if (DACR(FP_TG_CTRL) & 0x80000000) 2429 si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; 2430 si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; 2431 si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; 2433 si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_ [all...] |
H A D | nv_general.c | 1852 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff)); 1856 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00100000));
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/haiku/src/add-ons/accelerants/skeleton/engine/ |
H A D | crtc.c | 349 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 354 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 373 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 418 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 419 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 420 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 421 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 422 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 423 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 424 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG [all...] |
H A D | dac.c | 20 output = DACR(OUTPUT); 22 dac = DACR(TSTCTRL); 25 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 31 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 36 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 41 if (DACR(TSTCTRL) & 0x10000000) 53 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
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H A D | info.c | 2195 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2196 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2222 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2223 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2251 ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && 2268 if (DACR(FP_TG_CTRL) & 0x80000000) 2296 si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; 2297 si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; 2298 si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; 2300 si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_ [all...] |
H A D | dac2.c | 43 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 61 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
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/haiku/src/add-ons/accelerants/matrox/engine/ |
H A D | mga_dac.c | 140 LOG(2,("DAC: pixrdmsk 0x%02x\n", DACR(PIXRDMSK))); 162 if (DACR(PALWTADD)!=0) 175 R = DACR(PALDATA); 176 G = DACR(PALDATA); 177 B = DACR(PALDATA);
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/haiku/headers/private/graphics/matrox/ |
H A D | mga_macros.h | 316 #define DACR(A) (MGA_REG8(MGADAC_##A)) macro 320 #define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG))
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/haiku/headers/private/graphics/skeleton/ |
H A D | macros.h | 756 #define DACR(A) (ENG_RG32(ENDAC_##A)) macro
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/haiku/headers/private/graphics/via/ |
H A D | macros.h | 825 #define DACR(A) (ENG_REG32(ENDAC_##A)) macro
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/haiku/headers/private/graphics/nvidia/ |
H A D | nv_macros.h | 903 #define DACR(A) (NV_REG32(NVDAC_##A)) macro
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