1/* MGA registers definitions and macros for access to */ 2 3/* apsed : merged mga_macro.h and mga_regs.c with #define for speed */ 4 5/* PCI_config_space */ 6#define MGACFG_DEVID 0x00 7#define MGACFG_DEVCTRL 0x04 8#define MGACFG_CLASS 0x08 9#define MGACFG_HEADER 0x0c 10#define MGACFG_MGABASE2 0x10 11#define MGACFG_MGABASE1 0x14 12#define MGACFG_MGABASE3 0x18 // >= MYST 13#define MGACFG_SUBSYSIDR 0x2c // >= MYST 14#define MGACFG_ROMBASE 0x30 15#define MGACFG_CAP_PTR 0x34 // >= MIL2 16#define MGACFG_INTCTRL 0x3c 17#define MGACFG_OPTION 0x40 18#define MGACFG_MGA_INDEX 0x44 19#define MGACFG_MGA_DATA 0x48 20#define MGACFG_SUBSYSIDW 0x4c // >= MYST 21#define MGACFG_OPTION2 0x50 // >= G100 22#define MGACFG_OPTION3 0x54 // >= G400 23#define MGACFG_OPTION4 0x58 // >= G450 24#define MGACFG_PM_IDENT 0xdc // >= G100 25#define MGACFG_PM_CSR 0xe0 // >= G100 26#define MGACFG_AGP_IDENT 0xf0 // >= MIL2 27#define MGACFG_AGP_STS 0xf4 // >= MIL2 28#define MGACFG_AGP_CMD 0xf8 // >= MIL2 29 30/* VGA registers - these are byte wide */ 31#define MGAVGA_ATTR_I 0x1FC0 // apsed as SEQ 32#define MGAVGA_ATTR_D 0x1FC1 // apsed as SEQ 33#define MGAVGA_MISCW 0x1FC2 34#define MGAVGA_SEQ_I 0x1FC4 35#define MGAVGA_SEQ_D 0x1FC5 36#define MGAVGA_DACSTAT 0x1FC7 37#define MGAVGA_FEATR 0x1FCA 38#define MGAVGA_MISCR 0x1FCC 39#define MGAVGA_GCTL_I 0x1FCE 40#define MGAVGA_GCTL_D 0x1FCF 41#define MGAVGA_CRTC_I 0x1FD4 42#define MGAVGA_CRTC_D 0x1FD5 43#define MGAVGA_INSTS1 0x1FDA 44#define MGAVGA_FEATW 0x1FDA 45#define MGAVGA_CRTCEXT_I 0x1FDE 46#define MGAVGA_CRTCEXT_D 0x1FDF 47 48/* TVP3026 'non-std' DAC registers (>= MIL1) */ 49#define MGADAC_TVP_CUROVRWTADD 0x3c04 50#define MGADAC_TVP_CUROVRDATA 0x3c05 51#define MGADAC_TVP_CUROVRRDADD 0x3c07 52#define MGADAC_TVP_DIRCURCTRL 0x3c09 53#define MGADAC_TVP_CURRAMDATA 0x3c0b 54 55/* TVP3026 'non'std' (D)AC (X) (I)ndexed registers (>= MIL1) */ 56#define MGADXI_TVP_SILICONREV 0x01 57#define MGADXI_TVP_LATCHCTRL 0x0f 58#define MGADXI_TVP_TCOLCTRL 0x18 59#define MGADXI_TVP_CLOCKSEL 0x1a 60#define MGADXI_TVP_PALPAGE 0x1c 61#define MGADXI_TVP_PLLADDR 0x2c 62#define MGADXI_TVP_PIXPLLDATA 0x2d 63#define MGADXI_TVP_MEMPLLDATA 0x2e 64#define MGADXI_TVP_LOOPLLDATA 0x2f 65#define MGADXI_TVP_COLKEYOL 0x30 66#define MGADXI_TVP_COLKEYOH 0x31 67#define MGADXI_TVP_COLKEYRL 0x32 68#define MGADXI_TVP_COLKEYRH 0x33 69#define MGADXI_TVP_COLKEYGL 0x34 70#define MGADXI_TVP_COLKEYGH 0x35 71#define MGADXI_TVP_COLKEYBL 0x36 72#define MGADXI_TVP_COLKEYBH 0x37 73#define MGADXI_TVP_COLKEYCTRL 0x38 74#define MGADXI_TVP_MEMCLKCTRL 0x39 75#define MGADXI_TVP_TESTMODEDATA 0x3b 76#define MGADXI_TVP_ID 0x3f 77#define MGADXI_TVP_RESET 0xff 78 79/* DAC registers (>= G100) */ 80#define MGADAC_PALWTADD 0x3C00 81#define MGADAC_PALDATA 0x3C01 82#define MGADAC_PIXRDMSK 0x3C02 83#define MGADAC_PALRDADD 0x3C03 84#define MGADAC_X_DATAREG 0x3C0A 85#define MGADAC_CURSPOSXL 0x3C0C 86#define MGADAC_CURSPOSXH 0x3C0D 87#define MGADAC_CURSPOSYL 0x3C0E 88#define MGADAC_CURSPOSYH 0x3C0F 89 90/* (D)AC (X) (I)ndexed registers (>= G100) */ 91#define MGADXI_CURADDL 0x04 92#define MGADXI_CURADDH 0x05 93#define MGADXI_CURCTRL 0x06 94#define MGADXI_CURCOL0RED 0x08 95#define MGADXI_CURCOL0GREEN 0x09 96#define MGADXI_CURCOL0BLUE 0x0A 97#define MGADXI_CURCOL1RED 0x0C 98#define MGADXI_CURCOL1GREEN 0x0D 99#define MGADXI_CURCOL1BLUE 0x0E 100#define MGADXI_CURCOL2RED 0x10 101#define MGADXI_CURCOL2GREEN 0x11 102#define MGADXI_CURCOL2BLUE 0x12 103#define MGADXI_VREFCTRL 0x18 104#define MGADXI_MULCTRL 0x19 105#define MGADXI_PIXCLKCTRL 0x1A 106#define MGADXI_GENCTRL 0x1D 107#define MGADXI_MISCCTRL 0x1E 108#define MGADXI_PANELMODE 0x1F 109#define MGADXI_MAFCDEL 0x20 110#define MGADXI_GENIOCTRL 0x2A 111#define MGADXI_GENIODATA 0x2B 112#define MGADXI_SYSPLLM 0x2C 113#define MGADXI_SYSPLLN 0x2D 114#define MGADXI_SYSPLLP 0x2E 115#define MGADXI_SYSPLLSTAT 0x2F 116#define MGADXI_ZOOMCTRL 0x38 117#define MGADXI_SENSETEST 0x3A 118#define MGADXI_CRCREML 0x3C 119#define MGADXI_CRCREMH 0x3D 120#define MGADXI_CRCBITSEL 0x3E 121#define MGADXI_COLMSK 0x40 122#define MGADXI_COLKEY 0x42 123#define MGADXI_PIXPLLAM 0x44 124#define MGADXI_PIXPLLAN 0x45 125#define MGADXI_PIXPLLAP 0x46 126#define MGADXI_PIXPLLBM 0x48 127#define MGADXI_PIXPLLBN 0x49 128#define MGADXI_PIXPLLBP 0x4A 129#define MGADXI_PIXPLLCM 0x4C 130#define MGADXI_PIXPLLCN 0x4D 131#define MGADXI_PIXPLLCP 0x4E 132#define MGADXI_PIXPLLSTAT 0x4F 133#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/ 134 135/* (D)AC (X) (I)ndexed registers (>= G200) */ 136#define MGADXI_KEYOPMODE 0x51 137#define MGADXI_COLMSK0RED 0x52 138#define MGADXI_COLMSK0GREEN 0x53 139#define MGADXI_COLMSK0BLUE 0x54 140#define MGADXI_COLKEY0RED 0x55 141#define MGADXI_COLKEY0GREEN 0x56 142#define MGADXI_COLKEY0BLUE 0x57 143 144/* (D)AC (X) (I)ndexed registers (>= G450) */ 145#define MGADXI_TVO_IDX 0x87 146#define MGADXI_TVO_DATA 0x88 147#define MGADXI_OUTPUTCONN 0x8A 148#define MGADXI_SYNCCTRL 0x8B 149#define MGADXI_VIDPLLSTAT 0x8C 150#define MGADXI_VIDPLLP 0x8D 151#define MGADXI_VIDPLLM 0x8E 152#define MGADXI_VIDPLLN 0x8F 153#define MGADXI_PWRCTRL 0xA0 154#define MGADXI_PANMODE 0xA2 155 156/* MGA 1st CRTC registers */ 157#define MGACR1_VCOUNT 0x1E20 158 159/* MGA 2nd CRTC registers (>= G400) */ 160#define MGACR2_CTL 0x3C10 161#define MGACR2_HPARAM 0x3C14 162#define MGACR2_HSYNC 0x3C18 163#define MGACR2_VPARAM 0x3C1C 164#define MGACR2_VSYNC 0x3C20 165#define MGACR2_PRELOAD 0x3C24 166#define MGACR2_STARTADD0 0x3C28 167#define MGACR2_STARTADD1 0x3C2C 168#define MGACR2_OFFSET 0x3C40 169#define MGACR2_MISC 0x3C44 170#define MGACR2_VCOUNT 0x3C48 171#define MGACR2_DATACTL 0x3C4C 172 173/* MGA ACCeleration registers */ 174#define MGAACC_DWGCTL 0x1C00 175#define MGAACC_MACCESS 0x1C04 176#define MGAACC_MCTLWTST 0x1C08 177#define MGAACC_ZORG 0x1C0C 178#define MGAACC_PLNWT 0x1C1C 179#define MGAACC_BCOL 0x1C20 180#define MGAACC_FCOL 0x1C24 181#define MGAACC_XYSTRT 0x1C40 182#define MGAACC_XYEND 0x1C44 183#define MGAACC_SGN 0x1C58 184#define MGAACC_LEN 0x1C5C 185#define MGAACC_AR0 0x1C60 186#define MGAACC_AR3 0x1C6C 187#define MGAACC_AR5 0x1C74 188#define MGAACC_CXBNDRY 0x1C80 189#define MGAACC_FXBNDRY 0x1C84 190#define MGAACC_YDSTLEN 0x1C88 191#define MGAACC_PITCH 0x1C8C 192#define MGAACC_YDST 0x1C90 193#define MGAACC_YDSTORG 0x1C94 194#define MGAACC_YTOP 0x1C98 195#define MGAACC_YBOT 0x1C9C 196#define MGAACC_CXLEFT 0x1CA0 197#define MGAACC_CXRIGHT 0x1CA4 198#define MGAACC_FXLEFT 0x1CA8 199#define MGAACC_FXRIGHT 0x1CAC 200#define MGAACC_STATUS 0x1E14 201#define MGAACC_ICLEAR 0x1E18 /* required for interrupt stuff */ 202#define MGAACC_IEN 0x1E1C /* required for interrupt stuff */ 203#define MGAACC_RST 0x1E40 204#define MGAACC_MEMRDBK 0x1E44 205#define MGAACC_OPMODE 0x1E54 206#define MGAACC_PRIMADDRESS 0x1E58 207#define MGAACC_PRIMEND 0x1E5C 208#define MGAACC_TEXORG 0x2C24 // >= G100 209#define MGAACC_DWGSYNC 0x2C4C // >= G200 210#define MGAACC_TEXORG1 0x2CA4 // >= G200 211#define MGAACC_TEXORG2 0x2CA8 // >= G200 212#define MGAACC_TEXORG3 0x2CAC // >= G200 213#define MGAACC_TEXORG4 0x2CB0 // >= G200 214#define MGAACC_SRCORG 0x2CB4 // >= G200 215#define MGAACC_DSTORG 0x2CB8 // >= G200 216 217/*MGA BES (Back End Scaler) registers (>= G200) */ 218#define MGABES_A1ORG 0x3D00 219#define MGABES_A2ORG 0x3D04 220#define MGABES_B1ORG 0x3D08 221#define MGABES_B2ORG 0x3D0C 222#define MGABES_A1CORG 0x3D10 223#define MGABES_A2CORG 0x3D14 224#define MGABES_B1CORG 0x3D18 225#define MGABES_B2CORG 0x3D1C 226#define MGABES_CTL 0x3D20 227#define MGABES_PITCH 0x3D24 228#define MGABES_HCOORD 0x3D28 229#define MGABES_VCOORD 0x3D2C 230#define MGABES_HISCAL 0x3D30 231#define MGABES_VISCAL 0x3D34 232#define MGABES_HSRCST 0x3D38 233#define MGABES_HSRCEND 0x3D3C 234#define MGABES_LUMACTL 0x3D40 235#define MGABES_V1WGHT 0x3D48 236#define MGABES_V2WGHT 0x3D4C 237#define MGABES_HSRCLST 0x3D50 238#define MGABES_V1SRCLST 0x3D54 239#define MGABES_V2SRCLST 0x3D58 240#define MGABES_A1C3ORG 0x3D60 241#define MGABES_A2C3ORG 0x3D64 242#define MGABES_B1C3ORG 0x3D68 243#define MGABES_B2C3ORG 0x3D6C 244#define MGABES_GLOBCTL 0x3DC0 245#define MGABES_STATUS 0x3DC4 246 247/*MAVEN registers (<= G400) */ 248#define MGAMAV_PGM 0x3E 249#define MGAMAV_PIXPLLM 0x80 250#define MGAMAV_PIXPLLN 0x81 251#define MGAMAV_PIXPLLP 0x82 252#define MGAMAV_GAMMA1 0x83 253#define MGAMAV_GAMMA2 0x84 254#define MGAMAV_GAMMA3 0x85 255#define MGAMAV_GAMMA4 0x86 256#define MGAMAV_GAMMA5 0x87 257#define MGAMAV_GAMMA6 0x88 258#define MGAMAV_GAMMA7 0x89 259#define MGAMAV_GAMMA8 0x8A 260#define MGAMAV_GAMMA9 0x8B 261#define MGAMAV_MONSET 0x8C 262#define MGAMAV_TEST 0x8D 263#define MGAMAV_WREG_0X8E_L 0x8E 264#define MGAMAV_WREG_0X8E_H 0x8F 265#define MGAMAV_HSCALETV 0x90 266#define MGAMAV_TSCALETVL 0x91 267#define MGAMAV_TSCALETVH 0x92 268#define MGAMAV_FFILTER 0x93 269#define MGAMAV_MONEN 0x94 270#define MGAMAV_RESYNC 0x95 271#define MGAMAV_LASTLINEL 0x96 272#define MGAMAV_LASTLINEH 0x97 273#define MGAMAV_WREG_0X98_L 0x98 274#define MGAMAV_WREG_0X98_H 0x99 275#define MGAMAV_HSYNCLENL 0x9A 276#define MGAMAV_HSYNCLENH 0x9B 277#define MGAMAV_HSYNCSTRL 0x9C 278#define MGAMAV_HSYNCSTRH 0x9D 279#define MGAMAV_HDISPLAYL 0x9E 280#define MGAMAV_HDISPLAYH 0x9F 281#define MGAMAV_HTOTALL 0xA0 282#define MGAMAV_HTOTALH 0xA1 283#define MGAMAV_VSYNCLENL 0xA2 284#define MGAMAV_VSYNCLENH 0xA3 285#define MGAMAV_VSYNCSTRL 0xA4 286#define MGAMAV_VSYNCSTRH 0xA5 287#define MGAMAV_VDISPLAYL 0xA6 288#define MGAMAV_VDISPLAYH 0xA7 289#define MGAMAV_VTOTALL 0xA8 290#define MGAMAV_VTOTALH 0xA9 291#define MGAMAV_HVIDRSTL 0xAA 292#define MGAMAV_HVIDRSTH 0xAB 293#define MGAMAV_VVIDRSTL 0xAC 294#define MGAMAV_VVIDRSTH 0xAD 295#define MGAMAV_VSOMETHINGL 0xAE 296#define MGAMAV_VSOMETHINGH 0xAF 297#define MGAMAV_OUTMODE 0xB0 298#define MGAMAV_VERSION 0xB2 299#define MGAMAV_LOCK 0xB3 300#define MGAMAV_LUMA 0xB9 301#define MGAMAV_VDISPLAYTV 0xBE 302#define MGAMAV_STABLE 0xBF 303#define MGAMAV_HDISPLAYTV 0xC2 304#define MGAMAV_BREG_0XC6 0xC6 305 306/* Macros for convenient accesses to the MGA chips */ 307 308#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)] 309#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] 310 311/* read and write to PCI config space */ 312#define CFGR(A) (gx00_pci_access.offset=MGACFG_##A, ioctl(fd,GX00_GET_PCI, &gx00_pci_access,sizeof(gx00_pci_access)), gx00_pci_access.value) 313#define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access))) 314 315/* read and write from the dac registers */ 316#define DACR(A) (MGA_REG8(MGADAC_##A)) 317#define DACW(A,B) (MGA_REG8(MGADAC_##A)=B) 318 319/* read and write from the dac index register */ 320#define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG)) 321#define DXIW(A,B) (DACW(PALWTADD,MGADXI_##A),DACW(X_DATAREG,B)) 322 323/* read and write from the vga registers */ 324#define VGAR(A) (MGA_REG8(MGAVGA_##A)) 325#define VGAW(A,B) (MGA_REG8(MGAVGA_##A)=B) 326 327/* read and write from the indexed vga registers */ 328#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D)) 329#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C)) 330 331/* read and write from the powergraphics registers */ 332#define ACCR(A) (MGA_REG32(MGAACC_##A)) 333#define ACCW(A,B) (MGA_REG32(MGAACC_##A)=B) 334#define ACCGO(A,B) (MGA_REG32(MGAACC_##A + 0x0100)=B) 335 336/* read and write from the backend scaler registers */ 337#define BESR(A) (MGA_REG32(MGABES_##A)) 338#define BESW(A,B) (MGA_REG32(MGABES_##A)=B) 339 340/* read and write from first CRTC */ 341#define CR1R(A) (MGA_REG32(MGACR1_##A)) 342#define CR1W(A,B) (MGA_REG32(MGACR1_##A)=B) 343 344/* read and write from second CRTC */ 345#define CR2R(A) (MGA_REG32(MGACR2_##A)) 346#define CR2W(A,B) (MGA_REG32(MGACR2_##A)=B) 347 348/* read and write from maven (<= G400) */ 349#define MAVR(A) (i2c_maven_read (MGAMAV_##A )) 350#define MAVW(A,B) (i2c_maven_write(MGAMAV_##A ,B)) 351#define MAVRW(A) (i2c_maven_read (MGAMAV_##A )|(i2c_maven_read(MGAMAV_##A +1)<<8)) 352#define MAVWW(A,B) (i2c_maven_write(MGAMAV_##A ,B &0xFF),i2c_maven_write(MGAMAV_##A +1,B >>8)) 353