1/* registers definitions and macros for access to them */ 2 3/* PCI_config_space */ 4#define ENCFG_DEVID 0x00 5#define ENCFG_DEVCTRL 0x04 6#define ENCFG_CLASS 0x08 7#define ENCFG_HEADER 0x0c 8#define ENCFG_BASE1REGS 0x10 9#define ENCFG_BASE2FB 0x14 10#define ENCFG_BASE3 0x18 11#define ENCFG_BASE4 0x1c //unknown if used 12#define ENCFG_BASE5 0x20 //unknown if used 13#define ENCFG_BASE6 0x24 //unknown if used 14#define ENCFG_BASE7 0x28 //unknown if used 15#define ENCFG_SUBSYSID1 0x2c 16#define ENCFG_ROMBASE 0x30 17#define ENCFG_CAPPTR 0x34 18#define ENCFG_CFG_1 0x38 //unknown if used 19#define ENCFG_INTERRUPT 0x3c 20#define ENCFG_SUBSYSID2 0x40 21#define ENCFG_AGPREF 0x44 22#define ENCFG_AGPSTAT 0x48 23#define ENCFG_AGPCMD 0x4c 24#define ENCFG_ROMSHADOW 0x50 25#define ENCFG_VGA 0x54 26#define ENCFG_SCHRATCH 0x58 27#define ENCFG_CFG_10 0x5c 28#define ENCFG_CFG_11 0x60 29#define ENCFG_CFG_12 0x64 30#define ENCFG_CFG_13 0x68 //unknown if used 31#define ENCFG_CFG_14 0x6c //unknown if used 32#define ENCFG_CFG_15 0x70 //unknown if used 33#define ENCFG_CFG_16 0x74 //unknown if used 34#define ENCFG_CFG_17 0x78 //unknown if used 35#define ENCFG_CFG_18 0x7c //unknown if used 36#define ENCFG_CFG_19 0x80 //unknown if used 37#define ENCFG_CFG_20 0x84 //unknown if used 38#define ENCFG_CFG_21 0x88 //unknown if used 39#define ENCFG_CFG_22 0x8c //unknown if used 40#define ENCFG_CFG_23 0x90 //unknown if used 41#define ENCFG_CFG_24 0x94 //unknown if used 42#define ENCFG_CFG_25 0x98 //unknown if used 43#define ENCFG_CFG_26 0x9c //unknown if used 44#define ENCFG_CFG_27 0xa0 //unknown if used 45#define ENCFG_CFG_28 0xa4 //unknown if used 46#define ENCFG_CFG_29 0xa8 //unknown if used 47#define ENCFG_CFG_30 0xac //unknown if used 48#define ENCFG_CFG_31 0xb0 //unknown if used 49#define ENCFG_CFG_32 0xb4 //unknown if used 50#define ENCFG_CFG_33 0xb8 //unknown if used 51#define ENCFG_CFG_34 0xbc //unknown if used 52#define ENCFG_CFG_35 0xc0 //unknown if used 53#define ENCFG_CFG_36 0xc4 //unknown if used 54#define ENCFG_CFG_37 0xc8 //unknown if used 55#define ENCFG_CFG_38 0xcc //unknown if used 56#define ENCFG_CFG_39 0xd0 //unknown if used 57#define ENCFG_CFG_40 0xd4 //unknown if used 58#define ENCFG_CFG_41 0xd8 //unknown if used 59#define ENCFG_CFG_42 0xdc //unknown if used 60#define ENCFG_CFG_43 0xe0 //unknown if used 61#define ENCFG_CFG_44 0xe4 //unknown if used 62#define ENCFG_CFG_45 0xe8 //unknown if used 63#define ENCFG_CFG_46 0xec //unknown if used 64#define ENCFG_CFG_47 0xf0 //unknown if used 65#define ENCFG_CFG_48 0xf4 //unknown if used 66#define ENCFG_CFG_49 0xf8 //unknown if used 67#define ENCFG_CFG_50 0xfc //unknown if used 68 69/* used INT registers for vblank */ 70#define RG32_MAIN_INTE 0x00000140 71#define RG32_CRTC_INTS 0x00600100 72#define RG32_CRTC_INTE 0x00600140 73 74/* ACCeleration registers */ 75/* engine initialisation registers */ 76#define ENACC_FORMATS 0x00400618 77#define ENACC_OFFSET0 0x00400640 78#define ENACC_OFFSET1 0x00400644 79#define ENACC_OFFSET2 0x00400648 80#define ENACC_OFFSET3 0x0040064c 81#define ENACC_OFFSET4 0x00400650 82#define ENACC_OFFSET5 0x00400654 83#define ENACC_BBASE0 0x00400658 84#define ENACC_BBASE1 0x0040065c 85#define ENACC_BBASE2 0x00400660 86#define ENACC_BBASE3 0x00400664 87#define ENACC_NV10_BBASE4 0x00400668 88#define ENACC_NV10_BBASE5 0x0040066c 89#define ENACC_PITCH0 0x00400670 90#define ENACC_PITCH1 0x00400674 91#define ENACC_PITCH2 0x00400678 92#define ENACC_PITCH3 0x0040067c 93#define ENACC_PITCH4 0x00400680 94#define ENACC_BLIMIT0 0x00400684 95#define ENACC_BLIMIT1 0x00400688 96#define ENACC_BLIMIT2 0x0040068c 97#define ENACC_BLIMIT3 0x00400690 98#define ENACC_NV10_BLIMIT4 0x00400694 99#define ENACC_NV10_BLIMIT5 0x00400698 100#define ENACC_BPIXEL 0x00400724 101#define ENACC_NV20_OFFSET0 0x00400820 102#define ENACC_NV20_OFFSET1 0x00400824 103#define ENACC_NV20_OFFSET2 0x00400828 104#define ENACC_NV20_OFFSET3 0x0040082c 105#define ENACC_STRD_FMT 0x00400830 106#define ENACC_NV20_PITCH0 0x00400850 107#define ENACC_NV20_PITCH1 0x00400854 108#define ENACC_NV20_PITCH2 0x00400858 109#define ENACC_NV20_PITCH3 0x0040085c 110#define ENACC_NV20_BLIMIT6 0x00400864 111#define ENACC_NV20_BLIMIT7 0x00400868 112#define ENACC_NV20_BLIMIT8 0x0040086c 113#define ENACC_NV20_BLIMIT9 0x00400870 114#define ENACC_NV30_WHAT 0x00400890 115 116/* specials */ 117#define ENACC_DEBUG0 0x00400080 118#define ENACC_DEBUG1 0x00400084 119#define ENACC_DEBUG2 0x00400088 120#define ENACC_DEBUG3 0x0040008c 121#define ENACC_NV10_DEBUG4 0x00400090 122#define ENACC_ACC_INTS 0x00400100 123#define ENACC_ACC_INTE 0x00400140 124#define ENACC_NV10_CTX_CTRL 0x00400144 125#define ENACC_STATUS 0x00400700 126#define ENACC_NV04_SURF_TYP 0x0040070c 127#define ENACC_NV10_SURF_TYP 0x00400710 128#define ENACC_NV04_ACC_STAT 0x00400710 129#define ENACC_NV10_ACC_STAT 0x00400714 130#define ENACC_FIFO_EN 0x00400720 131#define ENACC_PAT_SHP 0x00400810 132#define ENACC_NV10_XFMOD0 0x00400f40 133#define ENACC_NV10_XFMOD1 0x00400f44 134#define ENACC_NV10_PIPEADR 0x00400f50 135#define ENACC_NV10_PIPEDAT 0x00400f54 136/* PGRAPH cache registers */ 137#define ENACC_CACHE1_1 0x00400160 138#define ENACC_CACHE1_2 0x00400180 139#define ENACC_CACHE1_3 0x004001a0 140#define ENACC_CACHE1_4 0x004001c0 141#define ENACC_CACHE1_5 0x004001e0 142#define ENACC_CACHE2_1 0x00400164 143#define ENACC_CACHE2_2 0x00400184 144#define ENACC_CACHE2_3 0x004001a4 145#define ENACC_CACHE2_4 0x004001c4 146#define ENACC_CACHE2_5 0x004001e4 147#define ENACC_CACHE3_1 0x00400168 148#define ENACC_CACHE3_2 0x00400188 149#define ENACC_CACHE3_3 0x004001a8 150#define ENACC_CACHE3_4 0x004001c8 151#define ENACC_CACHE3_5 0x004001e8 152#define ENACC_CACHE4_1 0x0040016c 153#define ENACC_CACHE4_2 0x0040018c 154#define ENACC_CACHE4_3 0x004001ac 155#define ENACC_CACHE4_4 0x004001cc 156#define ENACC_CACHE4_5 0x004001ec 157#define ENACC_NV10_CACHE5_1 0x00400170 158#define ENACC_NV04_CTX_CTRL 0x00400170 159#define ENACC_CACHE5_2 0x00400190 160#define ENACC_CACHE5_3 0x004001b0 161#define ENACC_CACHE5_4 0x004001d0 162#define ENACC_CACHE5_5 0x004001f0 163#define ENACC_NV10_CACHE6_1 0x00400174 164#define ENACC_CACHE6_2 0x00400194 165#define ENACC_CACHE6_3 0x004001b4 166#define ENACC_CACHE6_4 0x004001d4 167#define ENACC_CACHE6_5 0x004001f4 168#define ENACC_NV10_CACHE7_1 0x00400178 169#define ENACC_CACHE7_2 0x00400198 170#define ENACC_CACHE7_3 0x004001b8 171#define ENACC_CACHE7_4 0x004001d8 172#define ENACC_CACHE7_5 0x004001f8 173#define ENACC_NV10_CACHE8_1 0x0040017c 174#define ENACC_CACHE8_2 0x0040019c 175#define ENACC_CACHE8_3 0x004001bc 176#define ENACC_CACHE8_4 0x004001dc 177#define ENACC_CACHE8_5 0x004001fc 178#define ENACC_NV10_CTX_SW1 0x0040014c 179#define ENACC_NV10_CTX_SW2 0x00400150 180#define ENACC_NV10_CTX_SW3 0x00400154 181#define ENACC_NV10_CTX_SW4 0x00400158 182#define ENACC_NV10_CTX_SW5 0x0040015c 183/* engine tile registers src */ 184#define ENACC_NV20_FBWHAT0 0x00100200 185#define ENACC_NV20_FBWHAT1 0x00100204 186#define ENACC_NV10_FBTIL0AD 0x00100240 187#define ENACC_NV10_FBTIL0ED 0x00100244 188#define ENACC_NV10_FBTIL0PT 0x00100248 189#define ENACC_NV10_FBTIL0ST 0x0010024c 190#define ENACC_NV10_FBTIL1AD 0x00100250 191#define ENACC_NV10_FBTIL1ED 0x00100254 192#define ENACC_NV10_FBTIL1PT 0x00100258 193#define ENACC_NV10_FBTIL1ST 0x0010025c 194#define ENACC_NV10_FBTIL2AD 0x00100260 195#define ENACC_NV10_FBTIL2ED 0x00100264 196#define ENACC_NV10_FBTIL2PT 0x00100268 197#define ENACC_NV10_FBTIL2ST 0x0010026c 198#define ENACC_NV10_FBTIL3AD 0x00100270 199#define ENACC_NV10_FBTIL3ED 0x00100274 200#define ENACC_NV10_FBTIL3PT 0x00100278 201#define ENACC_NV10_FBTIL3ST 0x0010027c 202#define ENACC_NV10_FBTIL4AD 0x00100280 203#define ENACC_NV10_FBTIL4ED 0x00100284 204#define ENACC_NV10_FBTIL4PT 0x00100288 205#define ENACC_NV10_FBTIL4ST 0x0010028c 206#define ENACC_NV10_FBTIL5AD 0x00100290 207#define ENACC_NV10_FBTIL5ED 0x00100294 208#define ENACC_NV10_FBTIL5PT 0x00100298 209#define ENACC_NV10_FBTIL5ST 0x0010029c 210#define ENACC_NV10_FBTIL6AD 0x001002a0 211#define ENACC_NV10_FBTIL6ED 0x001002a4 212#define ENACC_NV10_FBTIL6PT 0x001002a8 213#define ENACC_NV10_FBTIL6ST 0x001002ac 214#define ENACC_NV10_FBTIL7AD 0x001002b0 215#define ENACC_NV10_FBTIL7ED 0x001002b4 216#define ENACC_NV10_FBTIL7PT 0x001002b8 217#define ENACC_NV10_FBTIL7ST 0x001002bc 218/* engine tile registers dst */ 219#define ENACC_NV20_WHAT0 0x004009a4 220#define ENACC_NV20_WHAT1 0x004009a8 221#define ENACC_NV10_TIL0AD 0x00400b00 222#define ENACC_NV10_TIL0ED 0x00400b04 223#define ENACC_NV10_TIL0PT 0x00400b08 224#define ENACC_NV10_TIL0ST 0x00400b0c 225#define ENACC_NV10_TIL1AD 0x00400b10 226#define ENACC_NV10_TIL1ED 0x00400b14 227#define ENACC_NV10_TIL1PT 0x00400b18 228#define ENACC_NV10_TIL1ST 0x00400b1c 229#define ENACC_NV10_TIL2AD 0x00400b20 230#define ENACC_NV10_TIL2ED 0x00400b24 231#define ENACC_NV10_TIL2PT 0x00400b28 232#define ENACC_NV10_TIL2ST 0x00400b2c 233#define ENACC_NV10_TIL3AD 0x00400b30 234#define ENACC_NV10_TIL3ED 0x00400b34 235#define ENACC_NV10_TIL3PT 0x00400b38 236#define ENACC_NV10_TIL3ST 0x00400b3c 237#define ENACC_NV10_TIL4AD 0x00400b40 238#define ENACC_NV10_TIL4ED 0x00400b44 239#define ENACC_NV10_TIL4PT 0x00400b48 240#define ENACC_NV10_TIL4ST 0x00400b4c 241#define ENACC_NV10_TIL5AD 0x00400b50 242#define ENACC_NV10_TIL5ED 0x00400b54 243#define ENACC_NV10_TIL5PT 0x00400b58 244#define ENACC_NV10_TIL5ST 0x00400b5c 245#define ENACC_NV10_TIL6AD 0x00400b60 246#define ENACC_NV10_TIL6ED 0x00400b64 247#define ENACC_NV10_TIL6PT 0x00400b68 248#define ENACC_NV10_TIL6ST 0x00400b6c 249#define ENACC_NV10_TIL7AD 0x00400b70 250#define ENACC_NV10_TIL7ED 0x00400b74 251#define ENACC_NV10_TIL7PT 0x00400b78 252#define ENACC_NV10_TIL7ST 0x00400b7c 253/* cache setup registers */ 254#define ENACC_PF_INTSTAT 0x00002100 255#define ENACC_PF_INTEN 0x00002140 256#define ENACC_PF_RAMHT 0x00002210 257#define ENACC_PF_RAMFC 0x00002214 258#define ENACC_PF_RAMRO 0x00002218 259#define ENACC_PF_CACHES 0x00002500 260#define ENACC_PF_SIZE 0x0000250c 261#define ENACC_PF_CACH0_PSH0 0x00003000 262#define ENACC_PF_CACH0_PUL0 0x00003050 263#define ENACC_PF_CACH0_PUL1 0x00003054 264#define ENACC_PF_CACH1_PSH0 0x00003200 265#define ENACC_PF_CACH1_PSH1 0x00003204 266#define ENACC_PF_CACH1_DMAI 0x0000322c 267#define ENACC_PF_CACH1_PUL0 0x00003250 268#define ENACC_PF_CACH1_PUL1 0x00003254 269#define ENACC_PF_CACH1_HASH 0x00003258 270/* Ptimer registers */ 271#define ENACC_PT_INTSTAT 0x00009100 272#define ENACC_PT_INTEN 0x00009140 273#define ENACC_PT_NUMERATOR 0x00009200 274#define ENACC_PT_DENOMINATR 0x00009210 275/* used PRAMIN registers */ 276#define ENACC_PR_CTX0_R 0x00711400 277#define ENACC_PR_CTX1_R 0x00711404 278#define ENACC_PR_CTX2_R 0x00711408 279#define ENACC_PR_CTX3_R 0x0071140c 280#define ENACC_PR_CTX0_0 0x00711420 281#define ENACC_PR_CTX1_0 0x00711424 282#define ENACC_PR_CTX2_0 0x00711428 283#define ENACC_PR_CTX3_0 0x0071142c 284#define ENACC_PR_CTX0_1 0x00711430 285#define ENACC_PR_CTX1_1 0x00711434 286#define ENACC_PR_CTX2_1 0x00711438 287#define ENACC_PR_CTX3_1 0x0071143c 288#define ENACC_PR_CTX0_2 0x00711440 289#define ENACC_PR_CTX1_2 0x00711444 290#define ENACC_PR_CTX2_2 0x00711448 291#define ENACC_PR_CTX3_2 0x0071144c 292#define ENACC_PR_CTX0_3 0x00711450 293#define ENACC_PR_CTX1_3 0x00711454 294#define ENACC_PR_CTX2_3 0x00711458 295#define ENACC_PR_CTX3_3 0x0071145c 296#define ENACC_PR_CTX0_4 0x00711460 297#define ENACC_PR_CTX1_4 0x00711464 298#define ENACC_PR_CTX2_4 0x00711468 299#define ENACC_PR_CTX3_4 0x0071146c 300#define ENACC_PR_CTX0_5 0x00711470 301#define ENACC_PR_CTX1_5 0x00711474 302#define ENACC_PR_CTX2_5 0x00711478 303#define ENACC_PR_CTX3_5 0x0071147c 304#define ENACC_PR_CTX0_6 0x00711480 305#define ENACC_PR_CTX1_6 0x00711484 306#define ENACC_PR_CTX2_6 0x00711488 307#define ENACC_PR_CTX3_6 0x0071148c 308#define ENACC_PR_CTX0_7 0x00711490 309#define ENACC_PR_CTX1_7 0x00711494 310#define ENACC_PR_CTX2_7 0x00711498 311#define ENACC_PR_CTX3_7 0x0071149c 312#define ENACC_PR_CTX0_8 0x007114a0 313#define ENACC_PR_CTX1_8 0x007114a4 314#define ENACC_PR_CTX2_8 0x007114a8 315#define ENACC_PR_CTX3_8 0x007114ac 316#define ENACC_PR_CTX0_9 0x007114b0 317#define ENACC_PR_CTX1_9 0x007114b4 318#define ENACC_PR_CTX2_9 0x007114b8 319#define ENACC_PR_CTX3_9 0x007114bc 320#define ENACC_PR_CTX0_A 0x007114c0 321#define ENACC_PR_CTX1_A 0x007114c4 /* not used */ 322#define ENACC_PR_CTX2_A 0x007114c8 323#define ENACC_PR_CTX3_A 0x007114cc 324#define ENACC_PR_CTX0_B 0x007114d0 325#define ENACC_PR_CTX1_B 0x007114d4 326#define ENACC_PR_CTX2_B 0x007114d8 327#define ENACC_PR_CTX3_B 0x007114dc 328#define ENACC_PR_CTX0_C 0x007114e0 329#define ENACC_PR_CTX1_C 0x007114e4 330#define ENACC_PR_CTX2_C 0x007114e8 331#define ENACC_PR_CTX3_C 0x007114ec 332#define ENACC_PR_CTX0_D 0x007114f0 333#define ENACC_PR_CTX1_D 0x007114f4 334#define ENACC_PR_CTX2_D 0x007114f8 335#define ENACC_PR_CTX3_D 0x007114fc 336#define ENACC_PR_CTX0_E 0x00711500 337#define ENACC_PR_CTX1_E 0x00711504 338#define ENACC_PR_CTX2_E 0x00711508 339#define ENACC_PR_CTX3_E 0x0071150c 340/* used RAMHT registers (hash-table(?)) */ 341#define ENACC_HT_HANDL_00 0x00710000 342#define ENACC_HT_VALUE_00 0x00710004 343#define ENACC_HT_HANDL_01 0x00710008 344#define ENACC_HT_VALUE_01 0x0071000c 345#define ENACC_HT_HANDL_02 0x00710010 346#define ENACC_HT_VALUE_02 0x00710014 347#define ENACC_HT_HANDL_03 0x00710018 348#define ENACC_HT_VALUE_03 0x0071001c 349#define ENACC_HT_HANDL_04 0x00710020 350#define ENACC_HT_VALUE_04 0x00710024 351#define ENACC_HT_HANDL_05 0x00710028 352#define ENACC_HT_VALUE_05 0x0071002c 353#define ENACC_HT_HANDL_06 0x00710030 354#define ENACC_HT_VALUE_06 0x00710034 355#define ENACC_HT_HANDL_10 0x00710080 356#define ENACC_HT_VALUE_10 0x00710084 357#define ENACC_HT_HANDL_11 0x00710088 358#define ENACC_HT_VALUE_11 0x0071008c 359#define ENACC_HT_HANDL_12 0x00710090 360#define ENACC_HT_VALUE_12 0x00710094 361#define ENACC_HT_HANDL_13 0x00710098 362#define ENACC_HT_VALUE_13 0x0071009c 363#define ENACC_HT_HANDL_14 0x007100a0 364#define ENACC_HT_VALUE_14 0x007100a4 365#define ENACC_HT_HANDL_15 0x007100a8 366#define ENACC_HT_VALUE_15 0x007100ac 367#define ENACC_HT_HANDL_16 0x007100b0 368#define ENACC_HT_VALUE_16 0x007100b4 369#define ENACC_HT_HANDL_17 0x007100b8 370#define ENACC_HT_VALUE_17 0x007100bc 371 372/* acc engine fifo setup registers (for function_register 'mappings') */ 373#define ENACC_FIFO_00800000 0x00800000 374#define ENACC_FIFO_00802000 0x00802000 375#define ENACC_FIFO_00804000 0x00804000 376#define ENACC_FIFO_00806000 0x00806000 377#define ENACC_FIFO_00808000 0x00808000 378#define ENACC_FIFO_0080a000 0x0080a000 379#define ENACC_FIFO_0080c000 0x0080c000 380#define ENACC_FIFO_0080e000 0x0080e000 381 382/* ROP3 registers (Raster OPeration) */ 383#define RG16_ROP_FIFOFREE 0x00800010 /* little endian */ 384#define ENACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ 385 386/* clip registers */ 387#define RG16_CLP_FIFOFREE 0x00802010 /* little endian */ 388#define ENACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ 389#define ENACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ 390 391/* pattern registers */ 392#define RG16_PAT_FIFOFREE 0x00804010 /* little endian */ 393#define ENACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ 394#define ENACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ 395#define ENACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ 396#define ENACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ 397#define ENACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ 398 399/* blit registers */ 400#define RG16_BLT_FIFOFREE 0x00808010 /* little endian */ 401#define ENACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ 402#define ENACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ 403#define ENACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ 404 405/* used bitmap registers */ 406#define RG16_BMP_FIFOFREE 0x0080a010 /* little endian */ 407#define ENACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ 408#define ENACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ 409#define ENACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ 410 411/* PCI direct registers */ 412#define RG32_PWRUPCTRL 0x00000200 413#define RG32_DUALHEAD_CTRL 0x000010f0//verify!!! 414#define RG8_MISCW 0x000c03c2 415#define RG8_MISCR 0x000c03cc 416#define RG8_VSE2 0x000c03c3 417#define RG8_SEQIND 0x000c03c4 418#define RG16_SEQIND 0x000c03c4 419#define RG8_SEQDAT 0x000c03c5 420#define RG8_GRPHIND 0x000c03ce 421#define RG16_GRPHIND 0x000c03ce 422#define RG8_GRPHDAT 0x000c03cf 423 424/* bootstrap info registers */ 425#define RG32_NV4STRAPINFO 0x00100000 426#define RG32_PFB_CONFIG_0 0x00100200 427#define RG32_PFB_CONFIG_1 0x00100204 428#define RG32_NV10STRAPINFO 0x0010020c 429#define RG32_FB_MRS1 0x001002c0 430#define RG32_FB_MRS2 0x001002c8 431#define RG32_NVSTRAPINFO2 0x00101000 432 433/* registers needed for 'coldstart' */ 434#define RG32_PFB_DEBUG_0 0x00100080 435#define RG32_PFB_REFCTRL 0x00100210 436#define RG32_COREPLL 0x00680500 437#define RG32_MEMPLL 0x00680504 438#define RG32_PLL_CTRL 0x00680510 439#define RG32_COREPLL2 0x00680570 /* NV31, NV36 only */ 440#define RG32_MEMPLL2 0x00680574 /* NV31, NV36 only */ 441#define RG32_CONFIG 0x00600804 442 443/* primary head */ 444#define RG8_ATTRINDW 0x006013c0 445#define RG8_ATTRDATW 0x006013c0 446#define RG8_ATTRDATR 0x006013c1 447#define RG8_CRTCIND 0x006013d4 448#define RG16_CRTCIND 0x006013d4 449#define RG8_CRTCDAT 0x006013d5 450#define RG8_INSTAT1 0x006013da 451#define RG32_NV10FBSTADD32 0x00600800 452#define RG32_RASTER 0x00600808 453#define RG32_NV10CURADD32 0x0060080c 454#define RG32_CURCONF 0x00600810 455#define RG32_PANEL_PWR 0x0060081c 456#define RG32_FUNCSEL 0x00600860 457 458/* secondary head */ 459#define RG8_ATTR2INDW 0x006033c0 460#define RG8_ATTR2DATW 0x006033c0 461#define RG8_ATTR2DATR 0x006033c1 462#define RG8_CRTC2IND 0x006033d4 463#define RG16_CRTC2IND 0x006033d4 464#define RG8_CRTC2DAT 0x006033d5 465#define RG8_2INSTAT1 0x006033da//verify!!! 466#define RG32_NV10FB2STADD32 0x00602800 467#define RG32_RASTER2 0x00602808 468#define RG32_NV10CUR2ADD32 0x0060280c 469#define RG32_2CURCONF 0x00602810 470#define RG32_2PANEL_PWR 0x0060281c//verify!!! 471#define RG32_2FUNCSEL 0x00602860 472 473/* DAC direct registers (standard VGA palette RAM registers) */ 474/* primary head */ 475#define RG8_PALMASK 0x006813c6 476#define RG8_PALINDR 0x006813c7 477#define RG8_PALINDW 0x006813c8 478#define RG8_PALDATA 0x006813c9 479/* secondary head */ 480#define RG8_PAL2MASK 0x006833c6 481#define RG8_PAL2INDR 0x006833c7 482#define RG8_PAL2INDW 0x006833c8 483#define RG8_PAL2DATA 0x006833c9 484 485/* PCI direct DAC registers (32bit) */ 486/* primary head */ 487#define ENDAC_CURPOS 0x00680300 488#define ENDAC_PIXPLLC 0x00680508 489#define ENDAC_PLLSEL 0x0068050c 490#define ENDAC_OUTPUT 0x0068052c 491#define ENDAC_PIXPLLC2 0x00680578 492#define ENDAC_GENCTRL 0x00680600 493#define ENDAC_TSTCTRL 0x00680608 494#define ENDAC_TSTDATA 0x00680610 495#define ENDAC_TV_SETUP 0x00680700 496/* (flatpanel registers: confirmed for TNT2 and up) */ 497#define ENDAC_FP_VDISPEND 0x00680800 498#define ENDAC_FP_VTOTAL 0x00680804 499#define ENDAC_FP_VCRTC 0x00680808 500#define ENDAC_FP_VSYNC_S 0x0068080c 501#define ENDAC_FP_VSYNC_E 0x00680810 502#define ENDAC_FP_VVALID_S 0x00680814 503#define ENDAC_FP_VVALID_E 0x00680818 504#define ENDAC_FP_HDISPEND 0x00680820 505#define ENDAC_FP_HTOTAL 0x00680824 506#define ENDAC_FP_HCRTC 0x00680828 507#define ENDAC_FP_HSYNC_S 0x0068082c 508#define ENDAC_FP_HSYNC_E 0x00680830 509#define ENDAC_FP_HVALID_S 0x00680834 510#define ENDAC_FP_HVALID_E 0x00680838 511#define ENDAC_FP_CHKSUM 0x00680840 512#define ENDAC_FP_TST_CTRL 0x00680844 513#define ENDAC_FP_TG_CTRL 0x00680848 514#define ENDAC_FP_DEBUG0 0x00680880 515#define ENDAC_FP_DEBUG1 0x00680884 516#define ENDAC_FP_DEBUG2 0x00680888 517#define ENDAC_FP_DEBUG3 0x0068088c 518/* secondary head */ 519#define ENDAC2_CURPOS 0x00682300 520#define ENDAC2_PIXPLLC 0x00680520 521#define ENDAC2_OUTPUT 0x0068252c 522#define ENDAC2_PIXPLLC2 0x0068057c 523#define ENDAC2_GENCTRL 0x00682600 524#define ENDAC2_TSTCTRL 0x00682608 525#define ENDAC2_TV_SETUP 0x00682700 //verify!!! 526/* (flatpanel registers) */ 527#define ENDAC2_FP_VDISPEND 0x00682800 528#define ENDAC2_FP_VTOTAL 0x00682804 529#define ENDAC2_FP_VCRTC 0x00682808 530#define ENDAC2_FP_VSYNC_S 0x0068280c 531#define ENDAC2_FP_VSYNC_E 0x00682810 532#define ENDAC2_FP_VVALID_S 0x00682814 533#define ENDAC2_FP_VVALID_E 0x00682818 534#define ENDAC2_FP_HDISPEND 0x00682820 535#define ENDAC2_FP_HTOTAL 0x00682824 536#define ENDAC2_FP_HCRTC 0x00682828 537#define ENDAC2_FP_HSYNC_S 0x0068282c 538#define ENDAC2_FP_HSYNC_E 0x00682830 539#define ENDAC2_FP_HVALID_S 0x00682834 540#define ENDAC2_FP_HVALID_E 0x00682838 541#define ENDAC2_FP_CHKSUM 0x00682840 542#define ENDAC2_FP_TST_CTRL 0x00682844 543#define ENDAC2_FP_TG_CTRL 0x00682848 544#define ENDAC2_FP_DEBUG0 0x00682880 545#define ENDAC2_FP_DEBUG1 0x00682884 546#define ENDAC2_FP_DEBUG2 0x00682888 547#define ENDAC2_FP_DEBUG3 0x0068288c 548 549/* Nvidia CRTC indexed registers */ 550/* VGA standard registers: */ 551#define ENCRTCX_HTOTAL 0x00 552#define ENCRTCX_HDISPE 0x01 553#define ENCRTCX_HBLANKS 0x02 554#define ENCRTCX_HBLANKE 0x03 555#define ENCRTCX_HSYNCS 0x04 556#define ENCRTCX_HSYNCE 0x05 557#define ENCRTCX_VTOTAL 0x06 558#define ENCRTCX_OVERFLOW 0x07 559#define ENCRTCX_PRROWSCN 0x08 560#define ENCRTCX_MAXSCLIN 0x09 561#define ENCRTCX_VGACURCTRL 0x0a 562#define ENCRTCX_FBSTADDH 0x0c 563#define ENCRTCX_FBSTADDL 0x0d 564#define ENCRTCX_VSYNCS 0x10 565#define ENCRTCX_VSYNCE 0x11 566#define ENCRTCX_VDISPE 0x12 567#define ENCRTCX_PITCHL 0x13 568#define ENCRTCX_VBLANKS 0x15 569#define ENCRTCX_VBLANKE 0x16 570#define ENCRTCX_MODECTL 0x17 571#define ENCRTCX_LINECOMP 0x18 572/* Nvidia specific registers: */ 573#define ENCRTCX_REPAINT0 0x19 574#define ENCRTCX_REPAINT1 0x1a 575#define ENCRTCX_FIFO 0x1b 576#define ENCRTCX_LOCK 0x1f 577#define ENCRTCX_FIFO_LWM 0x20 578#define ENCRTCX_BUFFER 0x21 579#define ENCRTCX_LSR 0x25 580#define ENCRTCX_PIXEL 0x28 581#define ENCRTCX_HEB 0x2d 582#define ENCRTCX_CURCTL2 0x2f 583#define ENCRTCX_CURCTL1 0x30 584#define ENCRTCX_CURCTL0 0x31 585#define ENCRTCX_LCD 0x33 586#define ENCRTCX_RMA 0x38 587#define ENCRTCX_INTERLACE 0x39 588#define ENCRTCX_TREG 0x3d 589#define ENCRTCX_EXTRA 0x41 590#define ENCRTCX_OWNER 0x44 591#define ENCRTCX_FP_HTIMING 0x53 592#define ENCRTCX_FP_VTIMING 0x54 593#define ENCRTCX_0x59 0x59 594#define ENCRTCX_0x9f 0x9f 595 596/* Nvidia ATTRIBUTE indexed registers */ 597/* VGA standard registers: */ 598#define ENATBX_MODECTL 0x10 599#define ENATBX_OSCANCOLOR 0x11 600#define ENATBX_COLPLANE_EN 0x12 601#define ENATBX_HORPIXPAN 0x13 602#define ENATBX_COLSEL 0x14 603 604/* Nvidia SEQUENCER indexed registers */ 605/* VGA standard registers: */ 606#define ENSEQX_RESET 0x00 607#define ENSEQX_CLKMODE 0x01 608#define ENSEQX_MEMMODE 0x04 609 610/* Nvidia GRAPHICS indexed registers */ 611/* VGA standard registers: */ 612#define ENGRPHX_ENSETRESET 0x01 613#define ENGRPHX_DATAROTATE 0x03 614#define ENGRPHX_READMAPSEL 0x04 615#define ENGRPHX_MODE 0x05 616#define ENGRPHX_MISC 0x06 617#define ENGRPHX_BITMASK 0x08 618 619/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ 620#define ENBES_NV04_INTE 0x00680140 621#define ENBES_NV04_ISCALVH 0x00680200 622#define ENBES_NV04_CTRL_V 0x00680204 623#define ENBES_NV04_CTRL_H 0x00680208 624#define ENBES_NV04_OE_STATE 0x00680224 625#define ENBES_NV04_SU_STATE 0x00680228 626#define ENBES_NV04_RM_STATE 0x0068022c 627#define ENBES_NV04_DSTREF 0x00680230 628#define ENBES_NV04_DSTSIZE 0x00680234 629#define ENBES_NV04_FIFOTHRS 0x00680238 630#define ENBES_NV04_FIFOBURL 0x0068023c 631#define ENBES_NV04_COLKEY 0x00680240 632#define ENBES_NV04_GENCTRL 0x00680244 633#define ENBES_NV04_RED_AMP 0x00680280 634#define ENBES_NV04_GRN_AMP 0x00680284 635#define ENBES_NV04_BLU_AMP 0x00680288 636#define ENBES_NV04_SAT 0x0068028c 637/* buffer 0 */ 638#define ENBES_NV04_0BUFADR 0x0068020c 639#define ENBES_NV04_0SRCPTCH 0x00680214 640#define ENBES_NV04_0OFFSET 0x0068021c 641/* buffer 1 */ 642#define ENBES_NV04_1BUFADR 0x00680210 643#define ENBES_NV04_1SRCPTCH 0x00680218 644#define ENBES_NV04_1OFFSET 0x00680220 645 646/* Nvidia BES (Back End Scaler) registers (>= NV10) */ 647#define ENBES_NV10_INTE 0x00008140 648#define ENBES_NV10_BUFSEL 0x00008700 649#define ENBES_NV10_GENCTRL 0x00008704 650#define ENBES_NV10_COLKEY 0x00008b00 651/* buffer 0 */ 652#define ENBES_NV10_0BUFADR 0x00008900 653#define ENBES_NV10_0MEMMASK 0x00008908 654#define ENBES_NV10_0BRICON 0x00008910 655#define ENBES_NV10_0SAT 0x00008918 656#define ENBES_NV10_0OFFSET 0x00008920 657#define ENBES_NV10_0SRCSIZE 0x00008928 658#define ENBES_NV10_0SRCREF 0x00008930 659#define ENBES_NV10_0ISCALH 0x00008938 660#define ENBES_NV10_0ISCALV 0x00008940 661#define ENBES_NV10_0DSTREF 0x00008948 662#define ENBES_NV10_0DSTSIZE 0x00008950 663#define ENBES_NV10_0SRCPTCH 0x00008958 664/* buffer 1 */ 665#define ENBES_NV10_1BUFADR 0x00008904 666#define ENBES_NV10_1MEMMASK 0x0000890c 667#define ENBES_NV10_1BRICON 0x00008914 668#define ENBES_NV10_1SAT 0x0000891c 669#define ENBES_NV10_1OFFSET 0x00008924 670#define ENBES_NV10_1SRCSIZE 0x0000892c 671#define ENBES_NV10_1SRCREF 0x00008934 672#define ENBES_NV10_1ISCALH 0x0000893c 673#define ENBES_NV10_1ISCALV 0x00008944 674#define ENBES_NV10_1DSTREF 0x0000894c 675#define ENBES_NV10_1DSTSIZE 0x00008954 676#define ENBES_NV10_1SRCPTCH 0x0000895c 677/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ 678#define ENBES_DEC_GENCTRL 0x00001588 679 680//old: 681/*MAVEN registers (<= G400) */ 682#define ENMAV_PGM 0x3E 683#define ENMAV_PIXPLLM 0x80 684#define ENMAV_PIXPLLN 0x81 685#define ENMAV_PIXPLLP 0x82 686#define ENMAV_GAMMA1 0x83 687#define ENMAV_GAMMA2 0x84 688#define ENMAV_GAMMA3 0x85 689#define ENMAV_GAMMA4 0x86 690#define ENMAV_GAMMA5 0x87 691#define ENMAV_GAMMA6 0x88 692#define ENMAV_GAMMA7 0x89 693#define ENMAV_GAMMA8 0x8A 694#define ENMAV_GAMMA9 0x8B 695#define ENMAV_MONSET 0x8C 696#define ENMAV_TEST 0x8D 697#define ENMAV_WREG_0X8E_L 0x8E 698#define ENMAV_WREG_0X8E_H 0x8F 699#define ENMAV_HSCALETV 0x90 700#define ENMAV_TSCALETVL 0x91 701#define ENMAV_TSCALETVH 0x92 702#define ENMAV_FFILTER 0x93 703#define ENMAV_MONEN 0x94 704#define ENMAV_RESYNC 0x95 705#define ENMAV_LASTLINEL 0x96 706#define ENMAV_LASTLINEH 0x97 707#define ENMAV_WREG_0X98_L 0x98 708#define ENMAV_WREG_0X98_H 0x99 709#define ENMAV_HSYNCLENL 0x9A 710#define ENMAV_HSYNCLENH 0x9B 711#define ENMAV_HSYNCSTRL 0x9C 712#define ENMAV_HSYNCSTRH 0x9D 713#define ENMAV_HDISPLAYL 0x9E 714#define ENMAV_HDISPLAYH 0x9F 715#define ENMAV_HTOTALL 0xA0 716#define ENMAV_HTOTALH 0xA1 717#define ENMAV_VSYNCLENL 0xA2 718#define ENMAV_VSYNCLENH 0xA3 719#define ENMAV_VSYNCSTRL 0xA4 720#define ENMAV_VSYNCSTRH 0xA5 721#define ENMAV_VDISPLAYL 0xA6 722#define ENMAV_VDISPLAYH 0xA7 723#define ENMAV_VTOTALL 0xA8 724#define ENMAV_VTOTALH 0xA9 725#define ENMAV_HVIDRSTL 0xAA 726#define ENMAV_HVIDRSTH 0xAB 727#define ENMAV_VVIDRSTL 0xAC 728#define ENMAV_VVIDRSTH 0xAD 729#define ENMAV_VSOMETHINGL 0xAE 730#define ENMAV_VSOMETHINGH 0xAF 731#define ENMAV_OUTMODE 0xB0 732#define ENMAV_LOCK 0xB3 733#define ENMAV_LUMA 0xB9 734#define ENMAV_VDISPLAYTV 0xBE 735#define ENMAV_STABLE 0xBF 736#define ENMAV_HDISPLAYTV 0xC2 737#define ENMAV_BREG_0XC6 0xC6 738//end old. 739 740/* Macros for convenient accesses to the NV chips */ 741#define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] 742#define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] 743#define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2] 744 745/* read and write to PCI config space */ 746#define CFGR(A) (eng_pci_access.offset=ENCFG_##A, ioctl(fd,ENG_GET_PCI, &eng_pci_access,sizeof(eng_pci_access)), eng_pci_access.value) 747#define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) 748 749/* read and write from ISA I/O space */ 750#define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) 751#define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) 752#define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data) 753#define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data) 754 755/* read and write from the dac registers */ 756#define DACR(A) (ENG_RG32(ENDAC_##A)) 757#define DACW(A,B) (ENG_RG32(ENDAC_##A)=B) 758 759/* read and write from the secondary dac registers */ 760#define DAC2R(A) (ENG_RG32(ENDAC2_##A)) 761#define DAC2W(A,B) (ENG_RG32(ENDAC2_##A)=B) 762 763/* read and write from the backend scaler registers */ 764#define BESR(A) (ENG_RG32(ENBES_##A)) 765#define BESW(A,B) (ENG_RG32(ENBES_##A)=B) 766 767/* read and write from CRTC indexed registers */ 768#define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) 769#define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) 770 771/* read and write from second CRTC indexed registers */ 772#define CRTC2W(A,B)(ENG_REG16(RG16_CRTC2IND) = ((ENCRTCX_##A) | ((B) << 8))) 773#define CRTC2R(A) (ENG_REG8(RG8_CRTC2IND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTC2DAT)) 774 775/* read and write from ATTRIBUTE indexed registers */ 776#define ATBW(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATW) = (B)) 777#define ATBR(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATR)) 778 779/* read and write from ATTRIBUTE indexed registers */ 780#define ATB2W(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATW) = (B)) 781#define ATB2R(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATR)) 782 783/* read and write from SEQUENCER indexed registers */ 784#define SEQW(A,B)(ENG_REG16(RG16_SEQIND) = ((ENSEQX_##A) | ((B) << 8))) 785#define SEQR(A) (ENG_REG8(RG8_SEQIND) = (ENSEQX_##A), ENG_REG8(RG8_SEQDAT)) 786 787/* read and write from PCI GRAPHICS indexed registers */ 788#define GRPHW(A,B)(ENG_REG16(RG16_GRPHIND) = ((ENGRPHX_##A) | ((B) << 8))) 789#define GRPHR(A) (ENG_REG8(RG8_GRPHIND) = (ENGRPHX_##A), ENG_REG8(RG8_GRPHDAT)) 790 791/* read and write from the acceleration engine registers */ 792#define ACCR(A) (ENG_RG32(ENACC_##A)) 793#define ACCW(A,B) (ENG_RG32(ENACC_##A)=B) 794 795//old: 796/* read and write from maven (<= G400) */ 797#define MAVR(A) (i2c_maven_read (ENMAV_##A )) 798#define MAVW(A,B) (i2c_maven_write(ENMAV_##A ,B)) 799#define MAVRW(A) (i2c_maven_read (ENMAV_##A )|(i2c_maven_read(ENMAV_##A +1)<<8)) 800#define MAVWW(A,B) (i2c_maven_write(ENMAV_##A ,B &0xFF),i2c_maven_write(ENMAV_##A +1,B >>8)) 801