/fuchsia/zircon/system/dev/display/vim-display/ |
H A D | hdmitx_clk.cpp | 37 SET_BIT32(HHI, reg, 1, 1, 28); \ 38 SET_BIT32(HHI, reg, 0, 1, 28); \ 63 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, n, PLL_CNTL_M_BITS, PLL_CNTL_M_START); 66 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL1, m, PLL_CNTL1_DIV_FRAC_BITS, PLL_CNTL1_DIV_FRAC_START); 72 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x1, 1, 28); 73 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x0, 1, 28); 86 SET_BIT32(PRESET, PRESET0_REGISTER, 1, 1, 7); 89 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 19); 90 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15); 114 SET_BIT32(HH [all...] |
H A D | hdmitx.cpp | 91 SET_BIT32(CBUS, PAD_PULL_UP_EN_REG1, 0, 2, 21); 92 SET_BIT32(CBUS, PAD_PULL_UP_REG1, 0, 2, 21); 93 SET_BIT32(CBUS, P_PREG_PAD_GPIO1_EN_N, 3, 2, 21); 94 SET_BIT32(CBUS, PERIPHS_PIN_MUX_6, 3, 2, 29); 97 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0x0100, 16, 0); 100 SET_BIT32(HHI, HHI_GCLK_MPEG2, 1, 1, 4); 103 SET_BIT32(HHI, HHI_MEM_PD_REG0, 0, 8, 8); 117 SET_BIT32(HDMITX, 0x8, 1, 1, 15); 118 SET_BIT32(HDMITX, 0x18, 1, 1, 15); 386 SET_BIT32(VP [all...] |
H A D | hdmitx.h | 46 #define SET_BIT32(x, dest, value, count, start) \ macro
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/fuchsia/zircon/system/dev/display/astro-display/ |
H A D | vpu.cpp | 117 SET_BIT32(VPU, VPP_OFIFO_SIZE, 0xFFF, 0, 12); 120 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0x7, 12, 3); 144 SET_BIT32(VPU, VPP_WRAP_OSD1_MATRIX_EN_CTRL, 1, 0, 1); 165 SET_BIT32(VPU, VPP_WRAP_OSD2_MATRIX_EN_CTRL, 1, 0, 1); 186 SET_BIT32(VPU, VPP_WRAP_OSD3_MATRIX_EN_CTRL, 1, 0, 1); 212 SET_BIT32(VPU, VPP_POST2_MATRIX_EN_CTRL, 1, 0, 1); 215 SET_BIT32(VPU, VPP_MATRIX_CTRL, 1, 0, 1); 216 SET_BIT32(VPU, VPP_MATRIX_CTRL, 0, 8, 3); 233 SET_BIT32(VPU, VPP_MATRIX_CLIP, 0, 5, 3); 240 SET_BIT32(HH [all...] |
H A D | astro-clock.cpp | 57 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL3, 1, 31, 1); 151 SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1); 152 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, 0, 5); 153 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); 156 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_EN_HPLL_G12A, 1); 194 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1); 197 SET_BIT32(HHI, HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1); 209 SET_BIT32(HHI, HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1); 213 SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 19, 1); 214 SET_BIT32(HH [all...] |
H A D | aml-dsi-host.cpp | 32 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_DPI_FORMAT, 34 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, SUPPORTED_VENC_DATA_WIDTH, 36 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0, 158 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CNTL, 0x3, 4, 2); 160 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0xf, 0, 4); 162 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_SW_RESET, 0x0, 0, 4); 164 SET_BIT32(MIPI_DSI, MIPI_DSI_TOP_CLK_CNTL, 0x3, 0, 2); 188 SET_BIT32(MIPI_DSI, DW_DSI_LPCLK_CTRL, 1, LPCLK_CTRL_AUTOCLKLANE_CTRL, 1);
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H A D | osd.cpp | 160 SET_BIT32(VPU, DOLBY_PATH_CTRL, 0x3, 2, 2); 181 SET_BIT32(VPU, VPU_VIU_OSD1_CTRL_STAT, kHwOsdBlockEnable0, 0, 4); 252 SET_BIT32(VPU,VPU_VPP_OSD_HSC_PHASE_STEP, 254 SET_BIT32(VPU,VPU_VPP_OSD_HSC_INI_PHASE, 0, 0, 16); 255 SET_BIT32(VPU,VPU_VPP_OSD_VSC_PHASE_STEP, 297 SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0000, 0, 9); 302 SET_BIT32(VPU, VPU_VPP_OSD_SCALE_COEF_IDX, 0x0100, 0, 9);
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H A D | aml-mipi-phy.cpp | 138 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 1, PHY_CTRL_RST_START, PHY_CTRL_RST_BITS); 139 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 0, PHY_CTRL_RST_START, PHY_CTRL_RST_BITS); 206 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 0, 7, 1); 245 SET_BIT32(DSI_PHY, MIPI_DSI_PHY_CTRL, 1, 1, 1);
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H A D | dw-mipi-dsi.cpp | 120 SET_BIT32(MIPI_DSI, DW_DSI_CMD_MODE_CFG, 123 SET_BIT32(MIPI_DSI, DW_DSI_PCKHDL_CFG, 129 SET_BIT32(MIPI_DSI, DW_DSI_CMD_MODE_CFG, 132 SET_BIT32(MIPI_DSI, DW_DSI_PCKHDL_CFG,
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H A D | common.h | 13 #define SET_BIT32(x, dest, value, start, count) \ macro
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/fuchsia/zircon/kernel/dev/hdcp/amlogic_s912/ |
H A D | hdcp.c | 42 #define SET_BIT32(x, dest, value, count, start) \ macro 80 SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0x0100, 16, 0); 83 SET_BIT32(HHI, HHI_GCLK_MPEG2, 1, 1, 4); 86 SET_BIT32(HHI, HHI_MEM_PD_REG0, 0, 8, 8);
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