display/vim-display/hdmitx_clk.cpp

37                 SET_BIT32(HHI, reg, 1, 1, 28); \
38                 SET_BIT32(HHI, reg, 0, 1, 28); \
63     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, n, PLL_CNTL_M_BITS, PLL_CNTL_M_START);
66     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL1, m, PLL_CNTL1_DIV_FRAC_BITS, PLL_CNTL1_DIV_FRAC_START);
72     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x1, 1, 28);
73     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL, 0x0, 1, 28);
86         SET_BIT32(PRESET, PRESET0_REGISTER, 1, 1, 7);
89     SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 19);
90     SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15);
114         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 18);
116         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 18);
117         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 2, 16);
118         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15);
119         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 14,  0);
121         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, shift_sel, 2, 16);
122         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 15);
123         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, shift_val, 14,  0);
124         SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 0, 1, 15);
127     SET_BIT32(HHI, HHI_VID_PLL_CLK_DIV, 1, 1, 19);
134     SET_BIT32(VPU, VPU_VPU_VIU_VENC_MUX_CTRL, pll->viu_type, 2, (pll->viu_channel == 1) ? 0 : 2);
135     SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 3, 9);
136     SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 0, 7, 0);
137     SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, 1, 1, 8);
141     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od1 >> 1), 2, 21);
144     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od2 >> 1), 2, 23);
147     SET_BIT32(HHI, HHI_HDMI_PLL_CNTL2, (pll->od3 >> 1), 2, 19);
151     SET_BIT32(HHI, HHI_VID_CLK_CNTL, 0, 3, 16);   // select vid_pll_clk
152     SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->vid_clk_div == 0) ? 0 : (pll->vid_clk_div - 1), 8, 0);
153     SET_BIT32(HHI, HHI_VID_CLK_CNTL, 7, 3, 0);
155     SET_BIT32(HHI, HHI_HDMI_CLK_CNTL, (pll->hdmi_tx_pixel_div == 12) ?
157     SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 5);   //enable gate
161         SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->encp_div == 12) ?
163         SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 2);   //enable gate
164         SET_BIT32(HHI, HHI_VID_CLK_CNTL, 1, 1, 19);
167         SET_BIT32(HHI, HHI_VID_CLK_DIV, (pll->encp_div == 12) ?
169         SET_BIT32(HHI, HHI_VID_CLK_CNTL2, 1, 1, 0);   //enable gate
170         SET_BIT32(HHI, HHI_VID_CLK_CNTL, 1, 1, 19);