Searched refs:mcr (Results 1 - 25 of 37) sorted by relevance

12

/freebsd-9.3-release/sys/arm/arm/
H A Dcpufunc_asm_arm11.S51 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
53 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
54 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
61 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
62 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
63 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
67 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
86 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
87 mcr p1
[all...]
H A Dcpufunc_asm_arm8.S46 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
53 mcr p15, 0, r1, c15, c0, 0 /* Write clock register */
58 mcr p15, 0, r2, c15, c0, 0 /* Write clock register */
76 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
79 mcr p15, 0, r0, c2, c0, 0
82 mcr p15, 0, r0, c8, c7, 0
85 mcr p15, 0, r0, c7, c7, 0
98 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
102 mcr p15, 0, r0, c8, c7, 1 /* flush I+D tlb single entry */
109 mcr p1
[all...]
H A Dcpufunc_asm_armv4.S47 mcr p15, 0, r0, c8, c7, 0 /* flush I+D tlb */
51 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
55 mcr p15, 0, r0, c8, c6, 0 /* flush D tlb */
59 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
66 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
H A Dcpufunc_asm_sa1.S67 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
68 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
71 mcr p15, 0, r0, c2, c0, 0
74 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
77 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
93 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
94 mcr p15, 0, r0, c8, c5, 0 /* flush I tlb */
101 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
105 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
109 mcr p1
[all...]
H A Dcpufunc_asm_fa526.S43 mcr p15, 0, r1, c7, c14, 0 /* clean and invalidate D$ */
44 mcr p15, 0, r1, c7, c5, 0 /* invalidate I$ */
45 mcr p15, 0, r1, c7, c5, 6 /* invalidate BTB */
46 mcr p15, 0, r1, c7, c10, 4 /* drain write and fill buffer */
48 mcr p15, 0, r0, c2, c0, 0 /* Write the TTB */
51 mcr p15, 0, r1, c8, c7, 0 /* invalidate I+D TLB */
62 mcr p15, 0, r0, c8, c7, 1 /* flush Utlb single entry */
69 mcr p15, 0, r0, c8, c5, 1 /* flush Itlb single entry */
76 mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt*/
81 mcr p1
[all...]
H A Dcpufunc_asm_arm10.S49 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
51 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
58 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
59 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
63 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
86 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
87 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
110 mcr p1
[all...]
H A Dcpufunc_asm_xscale_c3.S147 mcr p15, 0, r0, c7, c5, 0 /* flush I cache (D cleaned below) */
159 mcr p15, 0, r3, c7, c14, 2 /* clean and invalidate */
168 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
180 1: mcr p15, 0, r0, c7, c14, 1 /* clean/invalidate L1 D cache entry */
182 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
189 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
201 1: mcr p15, 0, r0, c7, c10, 1 /* clean D cache entry */
202 mcr p15, 0, r0, c7, c5, 1 /* flush I cache single entry */
209 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
221 1: mcr p1
[all...]
H A Dcpufunc_asm_ixp12x0.S55 mcr p15, 0, r0, c2, c0, 0
58 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
66 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
H A Dcpufunc_asm_arm7tdmi.S54 mcr p15, 0, r1, c2, c0, 0
69 mcr p15, 0, r0, c8, c7, 0
73 mcr p15, 0, r0, c8, c7, 1
82 mcr p15, 0, r0, c7, c7, 0
H A Dcpufunc_asm_sa11x0.S89 mcr p15, 0, r0, c15, c2, 2 /* disable clock switching */
91 mcr p15, 0, r0, c15, c8, 2 /* wait for interrupt */
93 mcr p15, 0, r0, c15, c1, 2 /* re-enable clock switching */
113 mcr p15, 0, r0, c2, c0, 0
116 mcr p15, 0, r0, c8, c7, 0 /* flush the I+D tlb */
124 mcr p15, 0, r0, c9, c0, 0 /* drain read buffer */
H A Dcpufunc_asm_xscale.S146 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
147 mcr p15, 0, r0, c7, c10, 4 /* drain write and fill buffer */
154 mcr p15, 0, r0, c2, c0, 0
157 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLB */
160 mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ and BTB */
176 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
177 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
184 mcr p15, 0, r0, c7, c7, 0 /* flush I+D cache */
188 mcr p15, 0, r0, c7, c5, 0 /* flush I cache */
192 mcr p1
[all...]
H A Dcpufunc_asm_armv5.S50 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
52 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
75 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
76 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
80 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
90 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
99 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
106 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
123 mcr p1
[all...]
H A Dcpufunc_asm_arm9.S48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
58 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
80 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
81 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
125 mcr p1
[all...]
H A Dcpufunc_asm_armv5_ec.S60 mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
63 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
65 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
67 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
86 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
87 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
91 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
101 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
108 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
125 mcr p1
[all...]
H A Dcpufunc_asm.S98 mcr p15, 0, r0, c1, c0, 0
103 mcr p15, 0, r0, c3, c0, 0
167 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
169 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */
171 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */
172 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
175 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */
176 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */
H A Dcpufunc_asm_sheeva.S49 mcr p15, 0, r1, c7, c5, 0 /* Invalidate ICache */
53 mcr p15, 1, r1, c15, c9, 0 /* Clean L2 */
54 mcr p15, 1, r1, c15, c11, 0 /* Invalidate L2 */
59 mcr p15, 0, r1, c7, c10, 4 /* drain the write buffer */
61 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
63 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
91 mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
92 mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
104 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
133 mcr p1
[all...]
H A Dlocore.S135 mcr p15, 0, r2, c1, c0, 0
162 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
163 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
167 mcr p15, 0, r0, c3, c0, 0
171 mcr p15, 0, r0, c1, c0, 0
286 mcr 15, 0, r0, c1, c0, 0
H A Dswtch.S163 mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */
358 mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */
/freebsd-9.3-release/sys/dev/vte/
H A Dif_vte.c1232 uint16_t mcr; local
1237 mcr = CSR_READ_2(sc, VTE_MCR0);
1238 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
1240 mcr |= MCR0_FULL_DUPLEX;
1243 mcr |= MCR0_FC_ENB;
1251 mcr |= MCR0_FC_ENB;
1254 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1587 uint16_t mcr; local
1590 mcr = CSR_READ_2(sc, VTE_MCR1);
1591 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESE
1807 uint16_t mcr; local
1834 uint16_t mcr; local
1947 uint16_t mchash[4], mcr; local
[all...]
/freebsd-9.3-release/sys/dev/ubsec/
H A Dubsec.c646 struct ubsec_mcr *mcr; local
655 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
656 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
1777 struct ubsec_mcr *mcr; local
1789 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1792 mcr->mcr_pkts = htole16(1);
1793 mcr->mcr_flags = 0;
1794 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1795 mcr->mcr_ipktbuf.pb_addr = mcr
2147 struct ubsec_mcr *mcr; local
2349 struct ubsec_mcr *mcr; local
2547 struct ubsec_mcr *mcr; local
2763 ubsec_dump_mcr(struct ubsec_mcr *mcr) argument
[all...]
/freebsd-9.3-release/sys/dev/uart/
H A Duart_dev_ns8250.c349 uint8_t mcr; member in struct:ns8250_softc
407 ns8250->mcr = uart_getreg(bas, REG_MCR);
438 if (ns8250->mcr & MCR_DTR)
440 if (ns8250->mcr & MCR_RTS)
638 uint8_t lsr, mcr, ier; local
647 mcr = MCR_IE;
652 mcr |= MCR_DTR | MCR_RTS;
679 uart_setreg(bas, REG_MCR, mcr);
695 uart_setreg(bas, REG_MCR, mcr);
725 uart_setreg(bas, REG_MCR, mcr);
[all...]
/freebsd-9.3-release/sys/mips/cavium/
H A Duart_dev_oct16550.c388 uint8_t mcr; member in struct:oct16550_softc
445 oct16550->mcr = uart_getreg(bas, REG_MCR);
451 if (oct16550->mcr & MCR_DTR)
453 if (oct16550->mcr & MCR_RTS)
795 oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
797 oct16550->mcr |= MCR_DTR;
799 oct16550->mcr |= MCR_RTS;
800 uart_setreg(bas, REG_MCR, oct16550->mcr);
/freebsd-9.3-release/sys/netgraph/atm/
H A Dng_atm.h88 { "mcr", &ng_parse_uint32_type }, \
142 uint32_t mcr; /* UBR+: Minimum cell rate */ member in struct:ngm_atm_cpcs_init
166 { "mcr", &ng_parse_uint32_type }, \
/freebsd-9.3-release/sbin/atm/atmconfig/
H A Datmconfig.help206 abr <pcr> <mcr> <icr> <tbe> <nrm> <trm> <adtf> <rif> <rdf> <cdf>
/freebsd-9.3-release/sys/dev/cy/
H A Dcy.c1844 int mcr; local
1850 mcr = com->mcr_image;
1851 if (mcr & com->mcr_dtr)
1853 if (mcr & com->mcr_rts)
1878 mcr = com->mcr_image;
1880 mcr |= com->mcr_dtr;
1882 mcr &= ~com->mcr_dtr;
1884 mcr |= com->mcr_rts;
1886 mcr &= ~com->mcr_rts;
1889 com->mcr_image = mcr;
[all...]

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