Lines Matching refs:mcr
48 mcr p15, 0, r0, c2, c0, 0 /* load new TTB */
50 mcr p15, 0, r0, c8, c7, 0 /* invalidate I+D TLBs */
57 mcr p15, 0, r0, c8, c6, 1 /* flush D tlb single entry */
58 mcr p15, 0, r0, c8, c5, 1 /* flush I tlb single entry */
80 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
81 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
94 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
103 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
107 mcr p15, 0, ip, c7, c10, 2 /* Clean D cache SE with Set/Index */
125 mcr p15, 0, r0, c7, c10, 1 /* Clean D cache SE with VA */
141 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
161 mcr p15, 0, r0, c7, c6, 1 /* Invalidate D cache SE with VA */
177 mcr p15, 0, r0, c7, c5, 1 /* Invalidate I cache SE with VA */
178 mcr p15, 0, r0, c7, c14, 1 /* Purge D cache SE with VA */
191 mcr p15, 0, r0, c7, c5, 0 /* Flush I cache */
201 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
205 mcr p15, 0, ip, c7, c14, 2 /* Purge D cache SE with Set/Index */
227 mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
228 mcr p15, 0, r0, c2, c0, 0 /* set the new TTB */
229 mcr p15, 0, r0, c8, c7, 0 /* and flush the I+D tlbs */