1/* $NetBSD: cpufunc_asm.S,v 1.12 2003/09/06 09:14:52 rearnsha Exp $ */ 2 3/*- 4 * Copyright (c) 1997,1998 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.S 38 * 39 * Assembly functions for CPU / MMU / TLB specific operations 40 * 41 * Created : 30/01/97 42 * 43 */ 44 45#include <machine/asm.h> 46__FBSDID("$FreeBSD$"); 47 48 .text 49 .align 0 50 51ENTRY(cpufunc_nullop) 52 RET 53 54/* 55 * Generic functions to read the internal coprocessor registers 56 * 57 * Currently these registers are : 58 * c0 - CPU ID 59 * c5 - Fault status 60 * c6 - Fault address 61 * 62 */ 63 64ENTRY(cpufunc_id) 65 mrc p15, 0, r0, c0, c0, 0 66 RET 67 68ENTRY(cpu_get_control) 69 mrc p15, 0, r0, c1, c0, 0 70 RET 71 72ENTRY(cpu_read_cache_config) 73 mrc p15, 0, r0, c0, c0, 1 74 RET 75 76ENTRY(cpufunc_faultstatus) 77 mrc p15, 0, r0, c5, c0, 0 78 RET 79 80ENTRY(cpufunc_faultaddress) 81 mrc p15, 0, r0, c6, c0, 0 82 RET 83 84 85/* 86 * Generic functions to write the internal coprocessor registers 87 * 88 * 89 * Currently these registers are 90 * c1 - CPU Control 91 * c3 - Domain Access Control 92 * 93 * All other registers are CPU architecture specific 94 */ 95 96#if 0 /* See below. */ 97ENTRY(cpufunc_control) 98 mcr p15, 0, r0, c1, c0, 0 99 RET 100#endif 101 102ENTRY(cpufunc_domains) 103 mcr p15, 0, r0, c3, c0, 0 104 RET 105 106/* 107 * Generic functions to read/modify/write the internal coprocessor registers 108 * 109 * 110 * Currently these registers are 111 * c1 - CPU Control 112 * 113 * All other registers are CPU architecture specific 114 */ 115 116ENTRY(cpufunc_control) 117 mrc p15, 0, r3, c1, c0, 0 /* Read the control register */ 118 bic r2, r3, r0 /* Clear bits */ 119 eor r2, r2, r1 /* XOR bits */ 120 121 122 teq r2, r3 /* Only write if there is a change */ 123 mcrne p15, 0, r2, c1, c0, 0 /* Write new control register */ 124 mov r0, r3 /* Return old value */ 125 126 RET 127.Lglou: 128 .asciz "plop %p\n" 129 .align 0 130/* 131 * other potentially useful software functions are: 132 * clean D cache entry and flush I cache entry 133 * for the moment use cache_purgeID_E 134 */ 135 136/* Random odd functions */ 137 138/* 139 * Function to get the offset of a stored program counter from the 140 * instruction doing the store. This offset is defined to be the same 141 * for all STRs and STMs on a given implementation. Code based on 142 * section 2.4.3 of the ARM ARM (2nd Ed.), with modifications to work 143 * in 26-bit modes as well. 144 */ 145ENTRY(get_pc_str_offset) 146 mov ip, sp 147 stmfd sp!, {fp, ip, lr, pc} 148 sub fp, ip, #4 149 sub sp, sp, #4 150 mov r1, pc /* R1 = addr of following STR */ 151 mov r0, r0 152 str pc, [sp] /* [SP] = . + offset */ 153 ldr r0, [sp] 154 sub r0, r0, r1 155 ldmdb fp, {fp, sp, pc} 156 157/* Allocate and lock a cacheline for the specified address. */ 158 159#define CPWAIT_BRANCH \ 160 sub pc, pc, #4 161#define CPWAIT() \ 162 mrc p15, 0, r2, c2, c0, 0; \ 163 mov r2, r2; \ 164 CPWAIT_BRANCH 165 166ENTRY(arm_lock_cache_line) 167 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 168 mov r1, #1 169 mcr p15, 0, r1, c9, c2, 0 /* Enable data cache lock mode */ 170 CPWAIT() 171 mcr p15, 0, r0, c7, c2, 5 /* Allocate the cache line */ 172 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 173 mov r1, #0 174 str r1, [r0] 175 mcr p15, 0, r0, c7, c10, 4 /* Drain write buffer */ 176 mcr p15, 0, r1, c9, c2, 0 /* Disable data cache lock mode */ 177 CPWAIT() 178 RET 179