1129198Scognet/* $NetBSD: cpuswitch.S,v 1.41 2003/11/15 08:44:18 scw Exp $ */ 2129198Scognet 3139735Simp/*- 4129198Scognet * Copyright 2003 Wasabi Systems, Inc. 5129198Scognet * All rights reserved. 6129198Scognet * 7129198Scognet * Written by Steve C. Woodford for Wasabi Systems, Inc. 8129198Scognet * 9129198Scognet * Redistribution and use in source and binary forms, with or without 10129198Scognet * modification, are permitted provided that the following conditions 11129198Scognet * are met: 12129198Scognet * 1. Redistributions of source code must retain the above copyright 13129198Scognet * notice, this list of conditions and the following disclaimer. 14129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 15129198Scognet * notice, this list of conditions and the following disclaimer in the 16129198Scognet * documentation and/or other materials provided with the distribution. 17129198Scognet * 3. All advertising materials mentioning features or use of this software 18129198Scognet * must display the following acknowledgement: 19129198Scognet * This product includes software developed for the NetBSD Project by 20129198Scognet * Wasabi Systems, Inc. 21129198Scognet * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22129198Scognet * or promote products derived from this software without specific prior 23129198Scognet * written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27129198Scognet * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28129198Scognet * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29129198Scognet * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30129198Scognet * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31129198Scognet * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32129198Scognet * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33129198Scognet * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34129198Scognet * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35129198Scognet * POSSIBILITY OF SUCH DAMAGE. 36129198Scognet */ 37139735Simp/*- 38129198Scognet * Copyright (c) 1994-1998 Mark Brinicombe. 39129198Scognet * Copyright (c) 1994 Brini. 40129198Scognet * All rights reserved. 41129198Scognet * 42129198Scognet * This code is derived from software written for Brini by Mark Brinicombe 43129198Scognet * 44129198Scognet * Redistribution and use in source and binary forms, with or without 45129198Scognet * modification, are permitted provided that the following conditions 46129198Scognet * are met: 47129198Scognet * 1. Redistributions of source code must retain the above copyright 48129198Scognet * notice, this list of conditions and the following disclaimer. 49129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 50129198Scognet * notice, this list of conditions and the following disclaimer in the 51129198Scognet * documentation and/or other materials provided with the distribution. 52129198Scognet * 3. All advertising materials mentioning features or use of this software 53129198Scognet * must display the following acknowledgement: 54129198Scognet * This product includes software developed by Brini. 55129198Scognet * 4. The name of the company nor the name of the author may be used to 56129198Scognet * endorse or promote products derived from this software without specific 57129198Scognet * prior written permission. 58129198Scognet * 59129198Scognet * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 60129198Scognet * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 61129198Scognet * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62129198Scognet * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 63129198Scognet * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 64129198Scognet * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 65129198Scognet * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 66129198Scognet * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 67129198Scognet * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 68129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 69129198Scognet * SUCH DAMAGE. 70129198Scognet * 71129198Scognet * RiscBSD kernel project 72129198Scognet * 73129198Scognet * cpuswitch.S 74129198Scognet * 75129198Scognet * cpu switching functions 76129198Scognet * 77129198Scognet * Created : 15/10/94 78129198Scognet * 79129198Scognet */ 80129198Scognet 81137274Scognet#include "assym.s" 82137274Scognet 83129198Scognet#include <machine/asm.h> 84129198Scognet#include <machine/asmacros.h> 85129198Scognet#include <machine/armreg.h> 86129198Scognet__FBSDID("$FreeBSD$"); 87129198Scognet 88129198Scognet 89129198Scognet/* 90129198Scognet * New experimental definitions of IRQdisable and IRQenable 91129198Scognet * These keep FIQ's enabled since FIQ's are special. 92129198Scognet */ 93129198Scognet 94129198Scognet#define DOMAIN_CLIENT 0x01 95129198Scognet#define IRQdisable \ 96129198Scognet mrs r14, cpsr ; \ 97129198Scognet orr r14, r14, #(I32_bit) ; \ 98129198Scognet msr cpsr_c, r14 ; \ 99129198Scognet 100129198Scognet#define IRQenable \ 101129198Scognet mrs r14, cpsr ; \ 102129198Scognet bic r14, r14, #(I32_bit) ; \ 103129198Scognet msr cpsr_c, r14 ; \ 104129198Scognet 105129198Scognet/* 106129198Scognet * These are used for switching the translation table/DACR. 107129198Scognet * Since the vector page can be invalid for a short time, we must 108129198Scognet * disable both regular IRQs *and* FIQs. 109129198Scognet * 110129198Scognet * XXX: This is not necessary if the vector table is relocated. 111129198Scognet */ 112129198Scognet#define IRQdisableALL \ 113129198Scognet mrs r14, cpsr ; \ 114129198Scognet orr r14, r14, #(I32_bit | F32_bit) ; \ 115129198Scognet msr cpsr_c, r14 116129198Scognet 117129198Scognet#define IRQenableALL \ 118129198Scognet mrs r14, cpsr ; \ 119129198Scognet bic r14, r14, #(I32_bit | F32_bit) ; \ 120129198Scognet msr cpsr_c, r14 121129198Scognet 122129198Scognet.Lcurpcb: 123129198Scognet .word _C_LABEL(__pcpu) + PC_CURPCB 124129198Scognet.Lcpufuncs: 125129198Scognet .word _C_LABEL(cpufuncs) 126129198Scognet.Lblock_userspace_access: 127129198Scognet .word _C_LABEL(block_userspace_access) 128129198Scognet.Lcpu_do_powersave: 129129198Scognet .word _C_LABEL(cpu_do_powersave) 130171780Scognet.Lblocked_lock: 131171780Scognet .word _C_LABEL(blocked_lock) 132135655ScognetENTRY(cpu_throw) 133135655Scognet mov r5, r1 134129198Scognet 135135655Scognet /* 136137274Scognet * r5 = newtd 137135655Scognet */ 138129198Scognet 139137274Scognet ldr r7, [r5, #(TD_PCB)] /* r7 = new thread's PCB */ 140135655Scognet 141135655Scognet /* Switch to lwp0 context */ 142135655Scognet 143135655Scognet ldr r9, .Lcpufuncs 144135655Scognet mov lr, pc 145135655Scognet ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] 146135655Scognet ldr r0, [r7, #(PCB_PL1VEC)] 147135655Scognet ldr r1, [r7, #(PCB_DACR)] 148135655Scognet /* 149135655Scognet * r0 = Pointer to L1 slot for vector_page (or NULL) 150135655Scognet * r1 = lwp0's DACR 151135655Scognet * r5 = lwp0 152135655Scognet * r6 = exit func 153135655Scognet * r7 = lwp0's PCB 154135655Scognet * r9 = cpufuncs 155135655Scognet */ 156135655Scognet 157135655Scognet /* 158135655Scognet * Ensure the vector table is accessible by fixing up lwp0's L1 159135655Scognet */ 160135655Scognet cmp r0, #0 /* No need to fixup vector table? */ 161135655Scognet ldrne r3, [r0] /* But if yes, fetch current value */ 162135655Scognet ldrne r2, [r7, #(PCB_L1VEC)] /* Fetch new vector_page value */ 163135655Scognet mcr p15, 0, r1, c3, c0, 0 /* Update DACR for lwp0's context */ 164135655Scognet cmpne r3, r2 /* Stuffing the same value? */ 165135655Scognet strne r2, [r0] /* Store if not. */ 166135655Scognet 167135655Scognet#ifdef PMAP_INCLUDE_PTE_SYNC 168135655Scognet /* 169135655Scognet * Need to sync the cache to make sure that last store is 170135655Scognet * visible to the MMU. 171135655Scognet */ 172135655Scognet movne r1, #4 173135655Scognet movne lr, pc 174135655Scognet ldrne pc, [r9, #CF_DCACHE_WB_RANGE] 175135655Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 176135655Scognet 177135655Scognet /* 178135655Scognet * Note: We don't do the same optimisation as cpu_switch() with 179135655Scognet * respect to avoiding flushing the TLB if we're switching to 180135655Scognet * the same L1 since this process' VM space may be about to go 181135655Scognet * away, so we don't want *any* turds left in the TLB. 182135655Scognet */ 183135655Scognet 184135655Scognet /* Switch the memory to the new process */ 185135655Scognet ldr r0, [r7, #(PCB_PAGEDIR)] 186135655Scognet mov lr, pc 187135655Scognet ldr pc, [r9, #CF_CONTEXT_SWITCH] 188135655Scognet 189135655Scognet /* Restore all the save registers */ 190172614Scognet#ifndef _ARM_ARCH_5E 191135655Scognet add r1, r7, #PCB_R8 192135655Scognet ldmia r1, {r8-r13} 193135655Scognet#else 194135655Scognet ldr r8, [r7, #(PCB_R8)] 195135655Scognet ldr r9, [r7, #(PCB_R9)] 196135655Scognet ldr r10, [r7, #(PCB_R10)] 197135655Scognet ldr r11, [r7, #(PCB_R11)] 198135655Scognet ldr r12, [r7, #(PCB_R12)] 199135655Scognet ldr r13, [r7, #(PCB_SP)] 200135655Scognet#endif 201135655Scognet 202138751Scognet /* We have a new curthread now so make a note it */ 203138751Scognet ldr r6, .Lcurthread 204138751Scognet str r5, [r6] 205135655Scognet 206142570Scognet /* Set the new tp */ 207142955Scognet ldr r6, [r5, #(TD_MD + MD_TP)] 208188540Scognet ldr r4, =ARM_TP_ADDRESS 209188540Scognet str r6, [r4] 210188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_START)] 211188540Scognet str r6, [r4, #4] /* ARM_RAS_START */ 212188540Scognet ldr r6, [r5, #(TD_MD + MD_RAS_END)] 213188581Scognet str r6, [r4, #8] /* ARM_RAS_END */ 214142570Scognet 215138751Scognet /* Hook in a new pcb */ 216138751Scognet ldr r6, .Lcurpcb 217138751Scognet str r7, [r6] 218138751Scognet 219138856Scognet ldmfd sp!, {r4-r7, pc} 220138751Scognet 221129198ScognetENTRY(cpu_switch) 222129198Scognet stmfd sp!, {r4-r7, lr} 223171780Scognet mov r6, r2 /* Save the mutex */ 224129198Scognet 225135655Scognet.Lswitch_resume: 226137274Scognet /* rem: r0 = old lwp */ 227129198Scognet /* rem: interrupts are disabled */ 228129198Scognet 229129198Scognet#ifdef MULTIPROCESSOR 230129198Scognet /* XXX use curcpu() */ 231137274Scognet ldr r2, .Lcpu_info_store 232137274Scognet str r2, [r6, #(L_CPU)] 233129198Scognet#endif 234129198Scognet 235129198Scognet /* Process is now on a processor. */ 236129198Scognet 237135655Scognet /* We have a new curthread now so make a note it */ 238129198Scognet ldr r7, .Lcurthread 239137274Scognet str r1, [r7] 240129198Scognet 241129198Scognet /* Hook in a new pcb */ 242129198Scognet ldr r7, .Lcurpcb 243137274Scognet ldr r2, [r1, #TD_PCB] 244137274Scognet str r2, [r7] 245129198Scognet 246137274Scognet /* rem: r1 = new process */ 247129198Scognet /* rem: interrupts are enabled */ 248129198Scognet 249129198Scognet /* Stage two : Save old context */ 250129198Scognet 251171780Scognet /* Get the user structure for the old thread. */ 252137274Scognet ldr r2, [r0, #(TD_PCB)] 253171780Scognet mov r4, r0 /* Save the old thread. */ 254129198Scognet 255171780Scognet /* Save all the registers in the old thread's pcb */ 256172614Scognet#ifndef _ARM_ARCH_5E 257137274Scognet add r7, r2, #(PCB_R8) 258129198Scognet stmia r7, {r8-r13} 259129198Scognet#else 260137274Scognet strd r8, [r2, #(PCB_R8)] 261137274Scognet strd r10, [r2, #(PCB_R10)] 262137274Scognet strd r12, [r2, #(PCB_R12)] 263129198Scognet#endif 264181144Scognet str pc, [r2, #(PCB_PC)] 265251866Sscottl 266129198Scognet /* 267129198Scognet * NOTE: We can now use r8-r13 until it is time to restore 268129198Scognet * them for the new process. 269129198Scognet */ 270142570Scognet /* Store the old tp */ 271175982Sraj ldr r3, =ARM_TP_ADDRESS 272188540Scognet ldr r9, [r3] 273142570Scognet str r9, [r0, #(TD_MD + MD_TP)] 274188540Scognet ldr r9, [r3, #4] 275188540Scognet str r9, [r0, #(TD_MD + MD_RAS_START)] 276188540Scognet ldr r9, [r3, #8] 277188540Scognet str r9, [r0, #(TD_MD + MD_RAS_END)] 278129198Scognet 279142570Scognet /* Set the new tp */ 280142570Scognet ldr r9, [r1, #(TD_MD + MD_TP)] 281188540Scognet str r9, [r3] 282188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_START)] 283188540Scognet str r9, [r3, #4] 284188540Scognet ldr r9, [r1, #(TD_MD + MD_RAS_END)] 285188540Scognet str r9, [r3, #8] 286129198Scognet 287129198Scognet /* Get the user structure for the new process in r9 */ 288137274Scognet ldr r9, [r1, #(TD_PCB)] 289129198Scognet 290137274Scognet /* r1 now free! */ 291137274Scognet 292138751Scognet mrs r3, cpsr 293129198Scognet /* 294251866Sscottl * We can do that, since 295138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 296129198Scognet */ 297138751Scognet orr r8, r3, #(PSR_UND32_MODE) 298138751Scognet msr cpsr_c, r8 299129198Scognet 300138751Scognet str sp, [r2, #(PCB_UND_SP)] 301129198Scognet 302129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 303129198Scognet /* rem: r8 = old PCB */ 304129198Scognet /* rem: r9 = new PCB */ 305129198Scognet /* rem: interrupts are enabled */ 306129198Scognet 307129198Scognet /* What else needs to be saved Only FPA stuff when that is supported */ 308129198Scognet 309129198Scognet /* Third phase : restore saved context */ 310129198Scognet 311129198Scognet /* rem: r8 = old PCB */ 312129198Scognet /* rem: r9 = new PCB */ 313129198Scognet /* rem: interrupts are enabled */ 314129198Scognet 315138414Scognet ldr r5, [r9, #(PCB_DACR)] /* r5 = new DACR */ 316138414Scognet mov r2, #DOMAIN_CLIENT 317138414Scognet cmp r5, r2, lsl #(PMAP_DOMAIN_KERNEL * 2) /* Sw to kernel thread? */ 318138414Scognet beq .Lcs_context_switched /* Yup. Don't flush cache */ 319138414Scognet mrc p15, 0, r0, c3, c0, 0 /* r0 = old DACR */ 320129198Scognet /* 321129198Scognet * Get the new L1 table pointer into r11. If we're switching to 322129198Scognet * an LWP with the same address space as the outgoing one, we can 323129198Scognet * skip the cache purge and the TTB load. 324129198Scognet * 325129198Scognet * To avoid data dep stalls that would happen anyway, we try 326129198Scognet * and get some useful work done in the mean time. 327129198Scognet */ 328138414Scognet mrc p15, 0, r10, c2, c0, 0 /* r10 = old L1 */ 329129198Scognet ldr r11, [r9, #(PCB_PAGEDIR)] /* r11 = new L1 */ 330129198Scognet 331129198Scognet 332129198Scognet teq r10, r11 /* Same L1? */ 333137274Scognet cmpeq r0, r5 /* Same DACR? */ 334129198Scognet beq .Lcs_context_switched /* yes! */ 335129198Scognet 336129198Scognet /* 337129198Scognet * Definately need to flush the cache. 338129198Scognet */ 339129198Scognet 340129198Scognet ldr r1, .Lcpufuncs 341129198Scognet mov lr, pc 342129198Scognet ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] 343129198Scognet.Lcs_cache_purge_skipped: 344171780Scognet /* rem: r6 = lock */ 345129198Scognet /* rem: r9 = new PCB */ 346129198Scognet /* rem: r10 = old L1 */ 347129198Scognet /* rem: r11 = new L1 */ 348129198Scognet 349129198Scognet mov r2, #0x00000000 350129198Scognet ldr r7, [r9, #(PCB_PL1VEC)] 351129198Scognet 352129198Scognet /* 353129198Scognet * Ensure the vector table is accessible by fixing up the L1 354129198Scognet */ 355129198Scognet cmp r7, #0 /* No need to fixup vector table? */ 356129198Scognet ldrne r2, [r7] /* But if yes, fetch current value */ 357129198Scognet ldrne r0, [r9, #(PCB_L1VEC)] /* Fetch new vector_page value */ 358137274Scognet mcr p15, 0, r5, c3, c0, 0 /* Update DACR for new context */ 359129198Scognet cmpne r2, r0 /* Stuffing the same value? */ 360135655Scognet#ifndef PMAP_INCLUDE_PTE_SYNC 361129198Scognet strne r0, [r7] /* Nope, update it */ 362129198Scognet#else 363129198Scognet beq .Lcs_same_vector 364129198Scognet str r0, [r7] /* Otherwise, update it */ 365129198Scognet 366129198Scognet /* 367129198Scognet * Need to sync the cache to make sure that last store is 368129198Scognet * visible to the MMU. 369129198Scognet */ 370129198Scognet ldr r2, .Lcpufuncs 371129198Scognet mov r0, r7 372129198Scognet mov r1, #4 373129198Scognet mov lr, pc 374129198Scognet ldr pc, [r2, #CF_DCACHE_WB_RANGE] 375129198Scognet 376129198Scognet.Lcs_same_vector: 377129198Scognet#endif /* PMAP_INCLUDE_PTE_SYNC */ 378129198Scognet 379129198Scognet cmp r10, r11 /* Switching to the same L1? */ 380129198Scognet ldr r10, .Lcpufuncs 381129198Scognet beq .Lcs_same_l1 /* Yup. */ 382129198Scognet /* 383129198Scognet * Do a full context switch, including full TLB flush. 384129198Scognet */ 385129198Scognet mov r0, r11 386129198Scognet mov lr, pc 387129198Scognet ldr pc, [r10, #CF_CONTEXT_SWITCH] 388129198Scognet 389129198Scognet b .Lcs_context_switched 390129198Scognet 391129198Scognet /* 392129198Scognet * We're switching to a different process in the same L1. 393129198Scognet * In this situation, we only need to flush the TLB for the 394129198Scognet * vector_page mapping, and even then only if r7 is non-NULL. 395129198Scognet */ 396129198Scognet.Lcs_same_l1: 397129198Scognet cmp r7, #0 398129198Scognet movne r0, #0 /* We *know* vector_page's VA is 0x0 */ 399129198Scognet movne lr, pc 400129198Scognet ldrne pc, [r10, #CF_TLB_FLUSHID_SE] 401138751Scognet /* 402251866Sscottl * We can do that, since 403138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 404138751Scognet */ 405129198Scognet 406129198Scognet.Lcs_context_switched: 407129198Scognet 408171780Scognet /* Release the old thread */ 409171780Scognet str r6, [r4, #TD_LOCK] 410171780Scognet ldr r6, .Lblocked_lock 411171780Scognet ldr r3, .Lcurthread 412171780Scognet ldr r3, [r3] 413171780Scognet 414171780Scognet1: 415171780Scognet ldr r4, [r3, #TD_LOCK] 416171780Scognet cmp r4, r6 417171780Scognet beq 1b 418171780Scognet 419129198Scognet /* XXXSCW: Safe to re-enable FIQs here */ 420129198Scognet 421129198Scognet /* rem: r9 = new PCB */ 422129198Scognet 423138751Scognet mrs r3, cpsr 424129198Scognet /* 425251866Sscottl * We can do that, since 426138751Scognet * PSR_SVC32_MODE|PSR_UND32_MODE == MSR_UND32_MODE 427129198Scognet */ 428138751Scognet orr r2, r3, #(PSR_UND32_MODE) 429138751Scognet msr cpsr_c, r2 430129198Scognet 431129198Scognet ldr sp, [r9, #(PCB_UND_SP)] 432129198Scognet 433129198Scognet msr cpsr_c, r3 /* Restore the old mode */ 434129198Scognet /* Restore all the save registers */ 435172614Scognet#ifndef _ARM_ARCH_5E 436129198Scognet add r7, r9, #PCB_R8 437129198Scognet ldmia r7, {r8-r13} 438129198Scognet sub r7, r7, #PCB_R8 /* restore PCB pointer */ 439129198Scognet#else 440129198Scognet mov r7, r9 441129198Scognet ldr r8, [r7, #(PCB_R8)] 442129198Scognet ldr r9, [r7, #(PCB_R9)] 443129198Scognet ldr r10, [r7, #(PCB_R10)] 444129198Scognet ldr r11, [r7, #(PCB_R11)] 445129198Scognet ldr r12, [r7, #(PCB_R12)] 446129198Scognet ldr r13, [r7, #(PCB_SP)] 447129198Scognet#endif 448129198Scognet 449171780Scognet /* rem: r6 = lock */ 450129198Scognet /* rem: r7 = new pcb */ 451129198Scognet 452129198Scognet#ifdef ARMFPE 453129198Scognet add r0, r7, #(USER_SIZE) & 0x00ff 454251866Sscottl add r0, r0, #(USER_SIZE) & 0xff00 455129198Scognet bl _C_LABEL(arm_fpe_core_changecontext) 456129198Scognet#endif 457129198Scognet 458129198Scognet /* rem: r5 = new lwp's proc */ 459171780Scognet /* rem: r6 = lock */ 460129198Scognet /* rem: r7 = new PCB */ 461129198Scognet 462129198Scognet.Lswitch_return: 463129198Scognet 464129198Scognet /* 465129198Scognet * Pull the registers that got pushed when either savectx() or 466129198Scognet * cpu_switch() was called and return. 467129198Scognet */ 468129198Scognet ldmfd sp!, {r4-r7, pc} 469129198Scognet#ifdef DIAGNOSTIC 470129198Scognet.Lswitch_bogons: 471129198Scognet adr r0, .Lswitch_panic_str 472129198Scognet bl _C_LABEL(panic) 473129198Scognet1: nop 474129198Scognet b 1b 475129198Scognet 476129198Scognet.Lswitch_panic_str: 477129198Scognet .asciz "cpu_switch: sched_qs empty with non-zero sched_whichqs!\n" 478129198Scognet#endif 479129198ScognetENTRY(savectx) 480150856Scognet stmfd sp!, {r4-r7, lr} 481150856Scognet /* 482150856Scognet * r0 = pcb 483150856Scognet */ 484150856Scognet /* Store all the registers in the process's pcb */ 485150856Scognet add r2, r0, #(PCB_R8) 486150856Scognet stmia r2, {r8-r13} 487150856Scognet ldmfd sp!, {r4-r7, pc} 488150856Scognet 489129198ScognetENTRY(fork_trampoline) 490129198Scognet mov r1, r5 491129198Scognet mov r2, sp 492129198Scognet mov r0, r4 493137976Scognet mov fp, #0 494129198Scognet bl _C_LABEL(fork_exit) 495135655Scognet /* Kill irq"s */ 496135655Scognet mrs r0, cpsr 497157616Scognet orr r0, r0, #(I32_bit|F32_bit) 498135655Scognet msr cpsr_c, r0 499146596Scognet DO_AST 500129198Scognet PULLFRAME 501129198Scognet 502129198Scognet movs pc, lr /* Exit */ 503129198Scognet 504135655ScognetAST_LOCALS 505