1/*	$NetBSD: cpufunc_asm_sa11x0.S,v 1.3 2002/08/17 16:36:32 thorpej Exp $	*/
2
3/*-
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 *    must display the following acknowledgement:
19 *	This product includes software developed for the NetBSD Project by
20 *	Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 *    or promote products derived from this software without specific prior
23 *    written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 */
38
39#include <machine/asm.h>
40__FBSDID("$FreeBSD$");
41
42	.data
43	.global	_C_LABEL(sa11x0_idle_mem)
44_C_LABEL(sa11x0_idle_mem):
45	.word	0
46
47	.text
48
49	.align	5
50
51	/* We're now 32-byte aligned */
52
53.Lsa11x0_idle_mem:
54	.word	_C_LABEL(sa11x0_idle_mem)				/* 1 */
55
56/*
57 * sa11x0_cpusleep
58 *
59 * This is called when there is nothing on any of the run queues.
60 * We go into IDLE mode so that any IRQ or FIQ will awaken us.
61 */
62ENTRY(sa11x0_cpu_sleep)
63	ldr	r1, .Lsa11x0_idle_mem	/* get address of... */		/* 2 */
64	nop								/* 3 */
65	ldr	r1, [r1]		/* ...non-cacheable page */	/* 4 */
66	nop								/* 5 */
67
68	/*
69	 * SA-1110 manual, 9.5.2.1 (Entering Idle Mode) says that
70	 * to enter idle mode:
71	 *
72	 *	* Disable clock switching
73	 *	* Issue load from non-cacheable address
74	 *	* Issue "wait for interrupt"
75	 *
76	 * The 3-insn sequence must reside in the first 3 words
77	 * of a cache line.
78	 *
79	 * We must disable interrupts in the CPSR so that we can
80	 * re-enable clock switching before servicing interrupts.
81	 */
82
83	mrs	r3, cpsr_all						/* 6 */
84	orr	r2, r3, #(I32_bit|F32_bit)				/* 7 */
85	msr	cpsr_all, r2						/* 8 */
86
87	/* We're now 32-byte aligned */
88
89	mcr	p15, 0, r0, c15, c2, 2	/* disable clock switching */
90	ldr	r0, [r1]		/* load from non-cacheable address */
91	mcr	p15, 0, r0, c15, c8, 2	/* wait for interrupt */
92
93	mcr	p15, 0, r0, c15, c1, 2	/* re-enable clock switching */
94
95	/* Restore interrupts (which will cause them to be serviced). */
96	msr	cpsr_all, r3
97	RET
98
99
100/*
101 * This function is the same as sa110_context_switch for now, the plan
102 * is to make use of the process id register to avoid cache flushes.
103 */
104ENTRY(sa11x0_context_switch)
105	/*
106	 * CF_CACHE_PURGE_ID will *ALWAYS* be called prior to this.
107	 * Thus the data cache will contain only kernel data and the
108	 * instruction cache will contain only kernel code, and all
109	 * kernel mappings are shared by all processes.
110	 */
111
112	/* Write the TTB */
113	mcr	p15, 0, r0, c2, c0, 0
114
115	/* If we have updated the TTB we must flush the TLB */
116	mcr	p15, 0, r0, c8, c7, 0	/* flush the I+D tlb */
117
118	/* Make sure that pipeline is emptied */
119	mov	r0, r0
120	mov	r0, r0
121	RET
122
123ENTRY(sa11x0_drain_readbuf)
124	mcr	p15, 0, r0, c9, c0, 0		/* drain read buffer */
125	RET
126