Searched refs:Opc (Results 1 - 25 of 124) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp45 unsigned Opc = MI->getOpcode(); local
47 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
48 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
68 unsigned Opc = MI->getOpcode(); local
70 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
71 (Opc
86 unsigned Opc = 0, ZeroReg = 0; local
185 unsigned Opc = 0; local
226 unsigned Opc = 0; local
427 compareOpndSize(unsigned Opc, const MachineFunction &MF) const argument
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H A DMips16InstrInfo.cpp73 unsigned Opc = 0; local
77 Opc = Mips::MoveR3216;
80 Opc = Mips::Move32R16;
83 Opc = Mips::Mfhi16, SrcReg = 0;
87 Opc = Mips::Mflo16, SrcReg = 0;
90 assert(Opc && "Cannot copy registers");
92 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
109 unsigned Opc = 0; local
111 Opc = Mips::SwRxSpImmX16;
112 assert(Opc
125 unsigned Opc = 0; local
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H A DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member in struct:llvm::MipsAnalyzeImmediate::Inst
21 Inst(unsigned Opc, unsigned ImmOpnd);
H A DMipsSEInstrInfo.h68 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
82 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
85 unsigned Opc) const;
87 std::pair<bool, bool> compareOpndSize(unsigned Opc,
H A DMips16InstrInfo.h67 virtual unsigned getOppositeBranchOpc(unsigned Opc) const;
114 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const;
117 unsigned Opc) const;
H A DMipsInstrInfo.h81 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
128 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
130 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
H A DMips16ISelDAGToDAG.h26 std::pair<SDNode*, SDNode*> selectMULT(SDNode *N, unsigned Opc, SDLoc DL,
H A DMipsAnalyzeImmediate.cpp15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {}
88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) ||
89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
100 Seq[0].Opc = LUi;
H A DMips16ISelDAGToDAG.cpp45 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, argument
48 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
256 unsigned Opc = InFlag.getOpcode(); (void)Opc; local
257 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
258 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
345 bool isUncondBranchOpcode(int Opc) { argument
346 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
350 bool isCondBranchOpcode(int Opc) { argument
351 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc
355 isJumpTableBranchOpcode(int Opc) argument
361 isIndirectBranchOpcode(int Opc) argument
365 isPopOpcode(int Opc) argument
371 isPushOpcode(int Opc) argument
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H A DARMInstrInfo.h33 // Return the non-pre/post incrementing version of 'Opc'. Return 0
35 unsigned getUnindexedOpcode(unsigned Opc) const;
H A DARMInstrInfo.cpp53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
54 switch (Opc) {
125 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? local
129 TII.get(Opc), TempReg)
131 if (Opc == ARM::LDRcp)
137 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
139 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
142 if (Opc == ARM::PICADD)
H A DThumb1InstrInfo.h32 // Return the non-pre/post incrementing version of 'Opc'. Return 0
34 unsigned getUnindexedOpcode(unsigned Opc) const;
H A DThumb2InstrInfo.h33 // Return the non-pre/post incrementing version of 'Opc'. Return 0
35 unsigned getUnindexedOpcode(unsigned Opc) const;
H A DARMFastISel.cpp566 unsigned Opc; local
569 Opc = ARM::FCONSTD;
572 Opc = ARM::FCONSTS;
575 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
592 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; local
595 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
611 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; local
616 TII.get(Opc), ImmReg)
627 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; local
630 TII.get(Opc), ImmRe
687 unsigned Opc; local
724 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; local
740 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; local
807 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; local
981 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; local
1049 unsigned Opc; local
1181 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; local
1438 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; local
1667 unsigned Opc; local
1692 unsigned Opc; local
1837 unsigned Opc; local
1883 unsigned Opc; local
2698 uint32_t Opc : 16; member in struct:InstructionTable
2757 unsigned Opc = ITP->Opc; local
2842 unsigned Opc = ARM::MOVsr; local
2962 uint16_t Opc[2]; // ARM, Thumb. member in struct:__anon2327::FoldableLoadExtendsStruct
3025 unsigned Opc; local
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H A DARMISelDAGToDAG.cpp111 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
114 SDValue &Offset, SDValue &Opc);
116 SDValue &Opc) {
117 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
121 SDValue &Opc) {
122 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
126 SDValue &Opc) {
127 SelectAddrMode2Worker(N, Base, Offset, Opc);
128 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
141 SDValue &Offset, SDValue &Opc);
115 SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
120 SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
125 SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
299 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
468 SelectImmShifterOperand(SDValue N, SDValue &BaseReg, SDValue &Opc, bool CheckProfitability) argument
491 SelectRegShifterOperand(SDValue N, SDValue &BaseReg, SDValue &ShReg, SDValue &Opc, bool CheckProfitability) argument
571 SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
668 SelectAddrMode2Worker(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
806 SelectAddrMode2OffsetReg(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
842 SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
862 SelectAddrMode2OffsetImm(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
887 SelectAddrMode3(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc) argument
937 SelectAddrMode3Offset(SDNode *Op, SDValue N, SDValue &Offset, SDValue &Opc) argument
1242 SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg, SDValue &Opc) argument
1676 isVLDfixed(unsigned Opc) argument
1703 isVSTfixed(unsigned Opc) argument
1728 getVLDSTRegisterUpdateOpcode(unsigned Opc) argument
1836 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
1986 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
2154 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] : local
2218 unsigned Opc = Opcodes[OpcodeIndex]; local
2258 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument
2296 unsigned Opc = isSigned local
2536 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? local
2605 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2()) local
2725 unsigned Opc = Subtarget->isThumb() ? local
2752 unsigned Opc = 0; local
2772 unsigned Opc = 0; local
2792 unsigned Opc = 0; local
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp60 static bool IsConditionalBranch(int Opc) { argument
61 return (Opc == Hexagon::JMP_t) || (Opc == Hexagon::JMP_f)
62 || (Opc == Hexagon::JMP_tnew_t) || (Opc == Hexagon::JMP_fnew_t);
66 static bool IsUnconditionalJump(int Opc) { argument
67 return (Opc == Hexagon::JMP);
113 int Opc = MI->getOpcode(); local
114 if (IsConditionalBranch(Opc)) {
H A DHexagonSplitConst32AndConst64.cpp81 int Opc = MI->getOpcode(); local
82 if (Opc == Hexagon::CONST32_set) {
95 else if (Opc == Hexagon::CONST32_set_jt) {
108 else if (Opc == Hexagon::CONST32_Label) {
121 else if (Opc == Hexagon::CONST32_Int_Real) {
132 else if (Opc == Hexagon::CONST64_Int_Real) {
/freebsd-9.3-release/contrib/llvm/include/llvm/
H A DAutoUpgrade.h53 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
59 Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
/freebsd-9.3-release/contrib/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp107 unsigned Opc = MBBI->getOpcode(); local
108 switch (Opc) {
152 unsigned Opc;
154 Opc = getLEArOpcode(IsLP64);
156 Opc = isSub
171 Opc = isSub
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
209 unsigned Opc
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H A DX86ISelDAGToDAG.cpp185 SDNode *SelectGather(SDNode *N, unsigned Opc);
186 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
1562 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { argument
1574 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
1796 unsigned Opc = 0; local
1801 Opc = AtomicOpcTbl[Op][ConstantI8];
1803 Opc = AtomicOpcTbl[Op][I8];
1808 Opc = AtomicOpcTbl[Op][SextConstantI16];
1810 Opc = AtomicOpcTbl[Op][ConstantI16];
1812 Opc
1918 isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc, SDValue StoredVal, SelectionDAG *CurDAG, LoadSDNode* &LoadNode, SDValue &InputChain) argument
2003 getFusedLdStOpcode(EVT &LdVT, unsigned Opc) argument
2021 SelectGather(SDNode *Node, unsigned Opc) argument
2052 unsigned Opc, MOpc; local
2088 unsigned Opc; local
2132 unsigned Opc; local
2741 unsigned Opc = StoredVal->getOpcode(); local
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/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp111 virtual unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm);
432 unsigned Opc; local
456 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
459 Opc = (IsZExt ?
464 Opc = (IsZExt ?
467 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
471 Opc = PPC::LD;
477 Opc = PPC::LFS;
480 Opc
572 unsigned Opc; local
967 unsigned Opc; local
1056 unsigned Opc; local
1098 unsigned Opc; local
1611 unsigned Opc; local
1807 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD; local
2003 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI; local
2152 FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
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/freebsd-9.3-release/contrib/llvm/include/llvm/IR/
H A DInstrTypes.h194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
196 BinaryOperator *BO = Create(Opc, V1, V2, Name);
200 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
202 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB);
206 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
208 BinaryOperator *BO = Create(Opc, V1, V2, Name, I);
213 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
215 BinaryOperator *BO = Create(Opc, V1, V2, Name);
219 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, argument
221 BinaryOperator *BO = Create(Opc, V
225 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
232 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = �) argument
238 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
244 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
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/freebsd-9.3-release/contrib/llvm/utils/TableGen/
H A DFixedLenDecoderEmitter.cpp421 void SingletonExists(unsigned Opc) const;
439 unsigned Opc) const;
441 bool doesOpcodeNeedPredicate(unsigned Opc) const;
444 unsigned Opc) const;
447 unsigned Opc) const;
451 unsigned Opc) const;
460 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const;
461 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const;
819 unsigned Opc = decodeULEB128(Buffer);
831 << NumberedInstructions->at(Opc)
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/freebsd-9.3-release/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp666 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; local
667 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
678 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
683 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
688 assert(!(ImmS == 31 && !SF && Opc != BFM)
690 assert(!(ImmS == 63 && SF && Opc != BFM)
694 if (Opc == SBFM && ImmR == 0) {
697 } else if (Opc == UBFM && ImmR == 0) {
701 if (Opc == UBFM) {
718 switch (Opc) {
782 unsigned Opc = fieldFromInstruction(Insn, 30, 2); local
943 unsigned Opc = fieldFromInstruction(Insn, 22, 2); local
1128 unsigned Opc = Inst.getOpcode(); local
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