Lines Matching refs:Opc
666 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
667 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
678 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
683 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
688 assert(!(ImmS == 31 && !SF && Opc != BFM)
690 assert(!(ImmS == 63 && SF && Opc != BFM)
694 if (Opc == SBFM && ImmR == 0) {
697 } else if (Opc == UBFM && ImmR == 0) {
701 if (Opc == UBFM) {
718 switch (Opc) {
782 unsigned Opc = fieldFromInstruction(Insn, 30, 2);
803 // Exactly how we decode the MCInst's registers depends on the Opc and V
808 switch (Opc) {
824 switch (Opc) {
943 unsigned Opc = fieldFromInstruction(Insn, 22, 2);
947 if (Opc == 0 || (V == 1 && Opc == 2)) {
952 if (V == 0 && (Opc == 2 || Size == 3)) {
956 } else if (V == 1 && (Opc & 2)) {
975 if (Opc != 0 && (V != 1 || Opc != 2)) {
1128 unsigned Opc = Inst.getOpcode();
1129 switch (Opc) {
1134 switch (Opc) {
1154 switch (Opc) {
1173 switch (Opc) {
1193 switch (Opc) {
1212 switch (Opc) {
1232 switch (Opc) {
1251 switch (Opc) {
1271 switch (Opc) {
1290 switch (Opc) {
1309 switch (Opc) {
1328 switch (Opc) {
1347 switch (Opc) {
1366 switch (Opc) {
1384 switch (Opc) {
1402 switch (Opc) {
1420 switch (Opc) {
1436 } // End of switch (Opc)