1235633Sdim//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===// 2195340Sed// 3195340Sed// The LLVM Compiler Infrastructure 4195340Sed// 5195340Sed// This file is distributed under the University of Illinois Open Source 6195340Sed// License. See LICENSE.TXT for details. 7195340Sed// 8195340Sed//===----------------------------------------------------------------------===// 9195340Sed// 10195340Sed// This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11195340Sed// 12195340Sed//===----------------------------------------------------------------------===// 13195340Sed 14195340Sed#ifndef THUMB2INSTRUCTIONINFO_H 15195340Sed#define THUMB2INSTRUCTIONINFO_H 16195340Sed 17195340Sed#include "ARM.h" 18235633Sdim#include "ARMBaseInstrInfo.h" 19195340Sed#include "Thumb2RegisterInfo.h" 20195340Sed 21195340Sednamespace llvm { 22210299Sedclass ARMSubtarget; 23210299Sedclass ScheduleHazardRecognizer; 24195340Sed 25195340Sedclass Thumb2InstrInfo : public ARMBaseInstrInfo { 26195340Sed Thumb2RegisterInfo RI; 27195340Sedpublic: 28195340Sed explicit Thumb2InstrInfo(const ARMSubtarget &STI); 29195340Sed 30235633Sdim /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 31235633Sdim void getNoopForMachoTarget(MCInst &NopInst) const; 32235633Sdim 33198090Srdivacky // Return the non-pre/post incrementing version of 'Opc'. Return 0 34198090Srdivacky // if there is not such an opcode. 35198090Srdivacky unsigned getUnindexedOpcode(unsigned Opc) const; 36195340Sed 37210299Sed void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 38210299Sed MachineBasicBlock *NewDest) const; 39195340Sed 40210299Sed bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 41210299Sed MachineBasicBlock::iterator MBBI) const; 42210299Sed 43210299Sed void copyPhysReg(MachineBasicBlock &MBB, 44210299Sed MachineBasicBlock::iterator I, DebugLoc DL, 45210299Sed unsigned DestReg, unsigned SrcReg, 46210299Sed bool KillSrc) const; 47210299Sed 48195340Sed void storeRegToStackSlot(MachineBasicBlock &MBB, 49198090Srdivacky MachineBasicBlock::iterator MBBI, 50198090Srdivacky unsigned SrcReg, bool isKill, int FrameIndex, 51208599Srdivacky const TargetRegisterClass *RC, 52208599Srdivacky const TargetRegisterInfo *TRI) const; 53195340Sed 54195340Sed void loadRegFromStackSlot(MachineBasicBlock &MBB, 55198090Srdivacky MachineBasicBlock::iterator MBBI, 56198090Srdivacky unsigned DestReg, int FrameIndex, 57208599Srdivacky const TargetRegisterClass *RC, 58208599Srdivacky const TargetRegisterInfo *TRI) const; 59195340Sed 60198090Srdivacky /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 61198090Srdivacky /// such, whenever a client has an instance of instruction info, it should 62198090Srdivacky /// always be able to get register info as well (through this method). 63198090Srdivacky /// 64198090Srdivacky const Thumb2RegisterInfo &getRegisterInfo() const { return RI; } 65195340Sed}; 66210299Sed 67210299Sed/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 68210299Sed/// to llvm::getInstrPredicate except it returns AL for conditional branch 69210299Sed/// instructions which are "predicated", but are not in IT blocks. 70210299SedARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 71210299Sed 72210299Sed 73195340Sed} 74195340Sed 75195340Sed#endif // THUMB2INSTRUCTIONINFO_H 76