Searched refs:CSR_WRITE_2 (Results 1 - 25 of 67) sorted by relevance

123

/freebsd-9.3-release/sys/dev/ep/
H A Dif_ep.c141 CSR_WRITE_2(sc, EP_W0_EEPROM_COMMAND,
402 CSR_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
404 CSR_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
408 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);
411 CSR_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
417 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
418 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
427 CSR_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
429 CSR_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
430 CSR_WRITE_2(s
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H A Dif_ep_pccard.c166 CSR_WRITE_2(sc, EP_W0_ADDRESS_CFG, result & 0xc000);
175 CSR_WRITE_2(sc, EP_W0_PRODUCT_ID, sc->epb.prod_id);
182 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
184 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0xc040);
185 CSR_WRITE_2(sc, EP_COMMAND, RX_RESET);
186 CSR_WRITE_2(sc, EP_COMMAND, TX_RESET);
189 CSR_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
H A Dif_epreg.h63 #define GO_WINDOW(sc, x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x))
334 #define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \
/freebsd-9.3-release/sys/dev/bm/
H A Dif_bm.c171 CSR_WRITE_2(sc, BM_MII_CSR, val);
227 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
241 CSR_WRITE_2(sc, BM_TX_CONFIG, reg);
916 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
923 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
929 CSR_WRITE_2(sc, BM_RX_CONFIG, reg);
956 CSR_WRITE_2(sc, BM_HASHTAB0, hash[0]);
957 CSR_WRITE_2(sc, BM_HASHTAB1, hash[1]);
958 CSR_WRITE_2(sc, BM_HASHTAB2, hash[2]);
959 CSR_WRITE_2(s
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H A Dif_bmreg.h157 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/sn/
H A Dif_sn.c276 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, RCR_SOFTRESET);
278 CSR_WRITE_2(sc, RECV_CONTROL_REG_W, 0x0000);
282 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, 0x0000);
290 CSR_WRITE_2(sc, CONTROL_REG_W, (CTR_AUTO_RELEASE | CTR_TE_ENABLE |
296 CSR_WRITE_2(sc, CONFIG_REG_W, flags);
302 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_RESET);
325 CSR_WRITE_2(sc, TXMIT_CONTROL_REG_W, flags);
442 CSR_WRITE_2(sc, MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
492 CSR_WRITE_2(sc, POINTER_REG_W, PTR_AUTOINC | 0x0000);
498 CSR_WRITE_2(s
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H A Dif_snvar.h62 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-9.3-release/sys/dev/vx/
H A Dif_vx.c162 CSR_WRITE_2(sc, VX_COMMAND, GLOBAL_RESET);
179 CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND, EEPROM_CMD_RD
239 CSR_WRITE_2(sc, VX_COMMAND, RX_RESET);
241 CSR_WRITE_2(sc, VX_COMMAND, TX_RESET);
248 CSR_WRITE_2(sc, VX_COMMAND, SET_RD_0_MASK | S_CARD_FAILURE |
250 CSR_WRITE_2(sc, VX_COMMAND, SET_INTR_MASK | S_CARD_FAILURE |
259 CSR_WRITE_2(sc, VX_COMMAND, ACK_INTR | 0xff);
264 CSR_WRITE_2(sc, VX_COMMAND, RX_ENABLE);
265 CSR_WRITE_2(sc, VX_COMMAND, TX_ENABLE);
285 CSR_WRITE_2(s
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H A Dif_vxvar.h62 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/ex/
H A Dif_ex.c380 CSR_WRITE_2(sc, RCV_BAR, sc->rx_lower_limit);
382 CSR_WRITE_2(sc, RCV_STOP_REG, sc->rx_upper_limit | 0xfe);
383 CSR_WRITE_2(sc, XMT_BAR, sc->tx_lower_limit);
499 CSR_WRITE_2(sc, HOST_ADDR_REG, dest);
500 CSR_WRITE_2(sc, IO_PORT_REG, Transmit_CMD);
501 CSR_WRITE_2(sc, IO_PORT_REG, 0);
502 CSR_WRITE_2(sc, IO_PORT_REG, next);
503 CSR_WRITE_2(sc, IO_PORT_REG, data_len);
534 CSR_WRITE_2(sc, HOST_ADDR_REG,
536 CSR_WRITE_2(s
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H A Dif_exvar.h99 #define CSR_WRITE_2(sc, off, val) \ macro
/freebsd-9.3-release/sys/dev/xl/
H A Dif_xl.c405 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val);
570 CSR_WRITE_2(sc, XL_W0_EE_CMD,
573 CSR_WRITE_2(sc, XL_W0_EE_CMD,
642 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
683 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
705 CSR_WRITE_2(sc, XL_COMMAND,
714 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
735 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
822 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/vte/
H A Dif_vte.c176 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
200 CSR_WRITE_2(sc, VTE_MMWD, val);
201 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
257 CSR_WRITE_2(sc, VTE_MRICR, val);
265 CSR_WRITE_2(sc, VTE_MTICR, val);
1158 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
1254 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1339 CSR_WRITE_2(sc, VTE_MIER, 0);
1360 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1559 CSR_WRITE_2(s
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H A Dif_vtevar.h149 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/wi/
H A Dif_wi_pci.c153 CSR_WRITE_2(sc, WI_INT_EN, 0);
154 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
201 CSR_WRITE_2(sc, WI_PCICOR_OFF, WI_PCICOR_RESET);
204 CSR_WRITE_2(sc, WI_PCICOR_OFF, 0x0000);
219 CSR_WRITE_2(sc, WI_HFA384X_SWSUPPORT0_OFF, WI_PRISM2STA_MAGIC);
H A Dif_wi.c594 CSR_WRITE_2(sc, WI_INT_EN, 0);
595 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
601 CSR_WRITE_2(sc, WI_INT_EN, 0);
617 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
628 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
720 CSR_WRITE_2(sc, WI_INT_EN, 0);
1159 CSR_WRITE_2(sc, WI_INT_EN, 0);
1160 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
1326 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX);
1337 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/bwi/
H A Dbwimac.c216 CSR_WRITE_2(sc, data_reg, v);
229 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
233 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
277 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
352 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
369 CSR_WRITE_2(sc, 0x60e, 0);
370 CSR_WRITE_2(sc, 0x610, 0x8000);
371 CSR_WRITE_2(sc, 0x604, 0);
372 CSR_WRITE_2(sc, 0x606, 0x200);
396 CSR_WRITE_2(s
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H A Dbwirf.c199 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
200 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
218 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
249 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
253 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
352 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
578 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
784 CSR_WRITE_2(s
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H A Dbwiphy.c138 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
139 CSR_WRITE_2(sc, BWI_PHY_DATA, data);
147 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
442 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
452 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
489 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
536 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
560 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
568 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
722 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/an/
H A Dif_an.c357 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
358 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), 0xFFFF);
1233 CSR_WRITE_2(sc, AN_INT_EN(sc->mpi350), 0);
1236 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), ~AN_INTRS(sc->mpi350));
1239 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_MIC);
1248 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_LINKSTAT);
1253 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_RX);
1258 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX_CPY);
1263 CSR_WRITE_2(sc, AN_EVENT_ACK(sc->mpi350), AN_EV_TX);
1268 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/vge/
H A Dif_vgevar.h219 #define CSR_WRITE_2(sc, reg, val) \ macro
234 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
241 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-9.3-release/sys/dev/ste/
H A Dif_ste.c190 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
193 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
297 CSR_WRITE_2(sc, STE_MACCTL0, cfg);
394 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
447 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
448 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
449 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
450 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
551 CSR_WRITE_2(sc, STE_COUNTDOWN,
578 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/tx/
H A Dif_txvar.h132 #define CSR_WRITE_2(sc, reg, val) \ macro
/freebsd-9.3-release/sys/dev/tl/
H A Dif_tl.c377 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
390 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
417 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
431 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
434 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val);
445 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
461 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
481 CSR_WRITE_2(sc, TL_DIO_ADDR, reg);
500 CSR_WRITE_2(s
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/freebsd-9.3-release/sys/dev/stge/
H A Dif_stge.c400 CSR_WRITE_2(sc, STGE_EepromCtrl,
1317 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1325 CSR_WRITE_2(sc, STGE_IntEnable,
1514 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2021 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2022 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2023 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2065 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2072 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2097 CSR_WRITE_2(s
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